SNLS448A January 2013 – October 2015 DS100RT410
The DS100RT410 is a low-power 10-GbE 4-channel retimer. Each channel in the DS100RT410 operates independently. All channels include a continuous time linear equalizer (CTLE), clock and data recovery circuit (CDR) and a differential driver with programmable output voltage and de-emphasis. Each channel also has its own eye opening monitor (EOM) and configurable pseudo-random bit sequence (PRBS) pattern generator that can be used for debug purposes.
The DS100RT410 is configurable through a single SMBus port. The DS100RT410 can also act as an SMBus master to configure itself from an EEPROM.
The following sections describe the functionality of the various circuits and features within the DS100RT410.
The data path operation of the DS100RT410 comprises the functional sections as listed in the data path block diagram of Figure 3. The functional sections are as follows.
The signal detect circuit monitors the energy level on the receiver inputs and powers on or off the rest of the high speed data path if a signal is detected or not. By default, each channel allows the signal detect circuit to automatically power on or off the rest of the high speed data path depending on if a signal is present. The signal detect block can be manually controlled in the SMBus channel registers. This can be useful if it is desired manually force channels to be disabled.
The CTLE in the DS125DF410 is a fully adaptive equalizer with optional limiting stage. The CTLE adapts according to a figure of merit (FOM) calculation during the lock acquisition process. Once the CDR has locked and the CTLE has been adapted, the CTLE boost level will be frozen until a manual re-adapt command is issued or until the CDR re-enters the lock acquisition state. The CTLE is typically readapted by resetting the CDR. The CTLE consists of 4 stages, with each stage having 2-bit boost control. This allows for 256 different stage-boost combinations. The CTLE adaption algorithm allows the CTLE to adapt through 32 of these stage-boost combinations. These 32 stage-boost combinations comprise the EQ Table in the channel registers; see channel registers 0x40 through 0x5F. This EQ Table can be reprogrammed to support up to 32 of the 256 stage-boost settings.
CTLE boost levels are determined by summing the boosts levels of the four stages. Different stage-boost combinations that sum to the same number will have approximately the same boost level, but will result in a different shape for the EQ transfer function (boost curve).
The fourth stage in the CTLE can be programmed through the SMBus interface to become a limiting stage rather than a linear stage.
The DS100RT410 performs its clock and data recovery function by detecting the bit transitions in the incoming data stream and locking its internal VCO to the clock represented by the mean arrival times of these bit transitions. This process produces a recovered clock with jitter which is greatly reduced for jitter frequencies outside the bandwidth of the CDR phase-locked loop (PLL). This is the primary benefit of using the DS100RT410 in a system. It significantly reduces the jitter present in the data stream, in effect resetting the jitter budget for the system.
The output driver is capable of driving variable output voltages with variable amounts of analog de-emphasis. The output voltage and de-emphasis level can be configured by writing registers over the SMBus. The DS100RT410 cannot determine independently the appropriate output voltage or de-emphasis setting, so the user is responsible for configuring these parameters. They can be set for each channel independently.
An idealized transmit waveform with analog de-emphasis applied is listed in Figure 4.
The CTLE is a four-stage amplifier with an adjustable, quasi-high-pass transfer function on each stage. The overall frequency response of the CTLE is set by adjusting the boost of each stage independently. Each stage of the CTLE can be set to one of four boost settings. The amount of high-frequency boost supplied by each stage generally increases with increasing boost settings.
The CTLE can also be configured to adapt automatically to provide the optimum boost level for its input signal. Automatic adaptation of the CTLE only is the default mode of operation for the DS100RT410.
The differential output voltage of the DS100RT410 can be configured from a nominal setting of 600-mV peak-to-peak differential to a nominal setting of 1.3-V peak-to-peak differential, depending upon the application. The driver output voltage as set is the typical peak-to-peak differential output voltage with no de-emphasis enabled.
The output de-emphasis level of the DS100RT410 can be configured from a nominal setting of 0 dB to a nominal setting of –12 dB depending upon the application. Larger absolute values of the de-emphasis setting provide more pre-distortion of the output driver waveform, accentuating the high-frequency components of the output driver waveform relative to the low-frequency components. Greater values of de-emphasis can compensate for greater dispersion in the transmission media at the output of the DS100RT410. The output de-emphasis level as set is the typical value to which the output signal will settle following the de-emphasis pulse interval in dB relative to the output VOD.
In some applications, a longer rise and fall time for the output signal is desired. This can reduce electromagnetic interference (EMI) generated by fast switching waveforms. This is necessary in some applications for regulatory compliance. In others, it can reduce the crosstalk in the system.
The DS100RT410 can be configured to operate with a nominal rise/fall time corresponding to the maximum slew rate of the output drivers into the load capacitance. Alternatively, the DS100RT410 can be configured to operate with a slightly greater rise and fall time if desired. For the typical specifications on rise and fall time, see Electrical Characteristics.
The DS100RT410 can be used without using a reference clock and the input REFCLK_IN pin can be open. When register 0x36, bits [5:4] are set to 2’b00, the device operates without using a reference clock at
For 1-GbE applications, it is required to bypass the CDR by setting the override bit 5 of register 0x09 to 1, and set the data mux bits [7:5] to 3'b000 of register 0x1E.
When using ref_mode 3, the device uses an external 25-MHz clock. This mode of operation is set in register 0x36 bits [5:4] = 2'b11 and is the default setting. In ref_mode 3, the external reference clock is used to aid initial phase lock, and to determine when its VCO is properly phase-locked. An external oscillator should be used to generate a 2.5-V, 25-MHz reference signal which is connected to the DS100RT410 on the reference clock input pin (pin 19). The DS100RT410 does not include a crystal oscillator circuit, so a stand-alone external oscillator is required.
The reference clock speeds up the initial phase lock acquisition. The DS100RT410 is set to phase lock to a known data rate, or a constrained set of known data rates, and the digital circuitry in the DS100RT410 pre-configures the VCO frequency. This enables the DS100RT410 phase-lock to the incoming signal very quickly.
The reference clock is used to calibrate the VCO coarse tuning. However, the reference clock is not synchronous to the data stream, and the quality of the reference clock does not affect the jitter on the output retimed data. The retimed data clock for each channel is synchronous to the VCO internal to that channel of the DS100RT410.
The phase noise of the reference clock is not critical. Any commercially-available 25-MHz oscillator can provide an acceptable reference clock. The reference clock can be daisy-chained from one retimer to another so that only one reference oscillator is required in a system.
The register 0x2F, bit 1 is set to 1 by default, which disables the false lock detector. This bit must be set to 0 to enable the false lock detector function.
REFCLK_IN pin 19 is for reference clock input. A 25-MHz oscillator should be connected to pin 19. See Electrical Characteristics for the requirements on the 25-MHz clock. The frequency of the reference clock should always be 25 MHz no matter what data rate or mode of operation is used.
REFCLK_OUT pin 42 is the reference clock output pin. The DS100RT410 drives a buffered replica of the
25-MHz reference clock input on this output pin. If there are multiple DS100RT410 in the system, the REFCLK_OUT pin can be directly connected to the REFCLK_IN pin of another DS100RT410 in a daisy chain connection. The other option is to connect the external 25-MHz oscillator to a clock fanout buffer to distribute the 25-MHz clock to each DS100RT410, which ensures there is a reference clock for the DS100RT410.
When daisy chaining the device REFCLK_OUT to the REFCLK_IN of another device, the trace connection should be less than 1.5 inches (about 5-pF trace capacitance) and it is possible to cascade up to 9 devices. While in other systems with longer interconnecting trace or more capacitive loading, the daisy chain of multiple devices should be reduced. In a system which requires longer daisy chain, it is recommended to place an inverted gate after the sixth device. The pre-distorted duty cycle from the inverter allows longer daisy chain. A better approach is to break the long daisy chain into shorter chains, each driven by a buffer version of the clock distribution and with each chain kept to a maximum of 6 cascade devices. As an example, if there are 12 devices in the system, the daisy chain connections can be divided into two groups of 6 devices and PCB trace length for the reference clock output to input connection; each should be 1.5 inch or less.
The INT line is an open-drain, 3.3-V tolerant, LVCMOS active-low output. The INT lines from multiple DS100RT410 devices can be wired together and connected to an external controller.
The DS100RT410 generates an interrupt when it detects a loss of signal after previously detecting the presence of a signal, or when it detects loss of lock after previously detecting phase lock. These interrupts are always enabled. In addition, the horizontal eye opening/vertical eye opening (HEO/VEO) interrupt can be enabled using SMBus control for each channel independently. This interrupt is disabled by default. The thresholds for horizontal and vertical eye opening that will trigger the interrupt can be set using the SMBus control for each channel.
If any interrupt occurs, registers in the DS100RT410 latch in information about the event that caused the interrupt. This can then be read out by the controller over the SMBus.
Each channel of the DS100RT410 has an independent lock indication pin. These lock indication pins, LOCK_3, LOCK_2, LOCK_1, and LOCK_0, are pin 16, pin 21, pin 40, and pin 45 respectively. These pins are shared with the SMBus address strap lines. After the address values have been latched in on power-up, these lines revert to their lock indication function.
When the corresponding channel of the DS100RT410 is locked to the incoming data stream, the lock indication pin goes high. This pin can be used to drive an LED on the board, giving a visual indication of the lock status, or it can be connected to other circuitry which can interpret the lock status of the channel.
The DS100RT410 can be configured using two different methods.
The configuration mode is selected by the state of the EN_SMB pin (pin 20) when the DS100RT410 is powered-up. This pin should be either left floating or tied to the device VDD through an optional 1-kΩ resistor. The effect of each of these settings is listed in Table 1.
|EN_SMB PIN SETTING||CONFIGURATION MODE||DESCRIPTION||READ_EN PIN|
|Float||SMBus Master Mode||Device reads its configuration from an external EEPROM on power-up||Pull low to initiate reading configuration data from external EEPROM|
|High (1)||SMBus Slave Mode||Device is configured over the SMBus by an external controller||Tie low to enable proper address strapping on power-up|
In SMBus master mode the DS100RT410 reads its initial configuration from an external EEPROM upon power-up. A description of the operation of this mode appears in the DS100DF410EVK, DS110DF410EVK, DS125DF410EVM User's Guide (SNLU126).
Some of the pins of the DS100RT410 perform the same functions in SMBus master and SMBus slave mode. Once the DS100RT410 has finished reading its initial configuration from the external EEPROM in SMBus master mode it reverts to SMBus slave mode and can be further configured by an external controller over the SMBus. Two device pins initiate reading the configuration from the external EEPROM and indicate when the configuration read is complete.
These pins are meant to work together. When the DS100RT410 is powered up in SMBus master mode, it reads its configuration from the external EEPROM. This is triggered when the READ_EN pin goes low. When the DS100RT410 is finished reading its configuration from the external EEPROM, it drives its ALL_DONE pin low. In this mode, as the name suggests, the DS100RT410 acts as an SMBus master during the time it is reading its configuration from the external EEPROM. After the DS100RT410 has finished reading its configuration from the EEPROM, it releases control of the SMBus and becomes a SMBus slave. In applications where there is more than one DS100RT410 on the same SMBus, bus contention can result if more than one DS100RT410 tries to take command of the SMBus as the SMBus master at the same time. The READ_EN and ALL_DONE pins prevent this bus contention.
In a system where the DS100RT410 devices are meant to operate in SMBus master mode, the READ_EN pin of one retimer should be wired to the ALL_DONE pin of the next. The system should be designed so that the READ_EN pin of one (and only one) of the DS100RT410 devices in the system is driven low on power-up. This DS100RT410 will take command of the SMBus on power-up and will read its initial configuration from the external EEPROM. When it is finished reading its configuration, it will set its ALL_DONE pin low. This pin should be connected to the READ_EN pin of another DS100RT410. When this DS100RT410 senses its READ_EN pin driven low, it will take command of the SMBus and read its initial configuration from the external EEPROM, after which it will set its ALL_DONE pin low. By connecting the ALL_DONE pin of each DS100RT410 to the READ_EN pin of the next DS100RT410, each DS100RT410 can read its initial configuration from the EEPROM without causing bus contention.
For SMBus slave mode, the READ_EN pin must be tied low. Do not leave the READ_EN pin floating or tie it high.
A connection diagram with several DS100RT410 devices along with an external EEPROM and an external SMBus master is listed in Figure 5. The SMBus master must be prevented from trying to take control of the SMBus until the DS100RT410 devices have finished reading their initial configurations from the EEPROM.
In SMBus master mode after the DS100RT410 has finished reading its initial configuration from the external EEPROM it reverts to SMBus slave mode. In either mode the SMBus data and clock lines, SDA and SDC, are used. Also, in either mode, the SMBus address is latched in on the address strap lines on power-up. In SMBus slave mode, if the READ_EN pin is not tied low, the DS100RT410 will not latch in the address on its address strap lines. It will instead latch in an SMBus write address of 0x30 regardless of the state of the address strap lines. This is a test feature. Obviously a system with multiple retimers cannot operate properly if all the retimers are responding to the same SMBus address. Tie the READ_EN pin low when operating in SMBus slave mode to avoid this condition.
The DS100RT410 reads its SMBus address upon power-up from the SMBus address lines.
In either SMBus master or SMBus slave mode the DS100RT410 must be assigned an SMBus address. A unique address must be assigned to each device on the SMBus.
The SMBus address is latched into the DS100RT410 on power-up. The address is read in from the state of the <ADDR_[3:0]> lines (pins 16, 21, 40, and 45 respectively) upon power-up. In either SMBus mode these address lines are input pins on power-up.
The DS100RT410 can be configured with any of 16 SMBus addresses. The SMBus addressing scheme uses the least-significant bit of the SMBus address as the Read/Write_N address bit. When an SMBus device is addressed for writing, this bit is set to 0; for reading, to 1. Table 2 lists the write address setting for the DS100RT410 versus the values latched in on the address lines at power-up.
The address byte sent by the SMBus master over the SMBus is always 8 bits long. The least-significant bit indicates whether the address is for a write operation, in which the master will output data to the SMBus to be read by the slave, or a read operation, in which the slave will output data to the SMBus to be read by the master. if the least-significant bit is a 0, the address is for a write operation. If it is a 1, the address is for a read operation. Accordingly, SMBus addresses are sometimes referred to as seven-bit addresses. To produce the write address for the SMBus, the seven-bit address is left-shifted by one bit. To produce the read address, it is left shifted by one bit and the least-significant bit is set to 1. Table 2 lists the seven-bit addresses corresponding to each set of address line values.
When the DS100RT410 is used in SMBus slave mode, the READ_EN pin must be tied low. If it is tied high or floating, the DS100RT410 will not latch in its address from the address lines on power-up. When the READ_EN pin is tied high in SMBus slave mode (that is, when the EN_SMB pin (pin 20) is tied high), the DS100RT410 will revert to an SMBus write address of 0x30. This is a test feature. If there are multiple DS100RT410 devices on the same SMBus, they will all revert to an SMBus write address of 0x30, which can cause SMBus collisions and failure to access the DS100RT410 devices over the SMBus.
|ADDR_3||ADDR_2||ADDR_1||ADDR_0||SMBus WRITE ADDRESS||SEVEN-BIT SMBus ADDRESS|
Once the DS100RT410 has latched in its SMBus address, its registers can be read and written using the two pins of the SMBus interface, serial data (SDA) and serial data clock (SDC).
In both SMBus master and SMBus slave mode, the DS100RT410 is configured using the SMBus. The SMBus consists of two lines, the SDA or Serial Data line (pin 18) and the SDC or Serial Data Clock line (pin 17). In the DS100RT410 these pins are 3.3-V tolerant. The SDA and SDC lines are both open-drain. They require a pullup resistor to a supply voltage, which may be either 2.5 V or 3.3 V. A pullup resistor in the 2-kΩ to 5-kΩ range will provide reliable SMBus operation.
The SMBus is a standard communications bus for configuring simple systems. For a specification of the SMBus an description of its operation, see http://smbus.org/specs/.
Register 0x00, bits 7:4 and register 0x06, bits 3:0
In order to communicate with the DS100RT410 over the SMBus, it is necessary for the SMBus controller to know the address of the DS100RT410. The address strap observation bits in control/shared register 0x00 are primarily useful as a test of SMBus operation. There is no way to get the DS100RT410 to indicate what its SMBus address is unless it is already known.
In order to use the address strap observation bits of control/shared register 0x00, it is necessary first to set the diagnostic test control bits of control/shared register 0x06. This four-bit field should be written with a value of 0xa. When this value is written to bits 3:0 of control/shared register 0x06, then the value of the SMBus address straps can be read in register 0x00, bits 7:4. The value read will be the same as the value present on the ADDR3:ADDR0 lines when the DS100RT410 was powered up. For example, if a value of 0x1 is read from control/shared register 0x00, bits 7:4, then at power-up the ADDR0 line was set to 1 and the other address lines, ADDR3:ADDR1, were all set to 0. The DS100RT410 is set to an SMBus Write address of 0x32.
Control/shared register 0x01 contains the device revision and device ID. The device revision listed in Table 11 is the current revision for the DS100RT410. The device ID will be different for the different devices in the retimer family. The value listed in "For the DS100RT410, Register 0x01, bits 4:0 = 0x10" is the correct value for the DS100RT410. This register is useful because it can be interrogated by software to determine the device variant and revision installed in a particular system. The software might then configure the device with appropriate settings depending upon the device variant and revision.
Register 0x04, bit 6
Register 0x04, bit 6, clears all the control/shared registers back to their factory defaults. This bit is self-clearing, so it is cleared after it is written and the control/shared registers are reset to their factory default values.
Register 0x05, bits 3:0
The operation of these bits is described in Interrupt Status.
Register 0x04, bits 5 and 4 and register 0x05, bits 7 and 4
Register 0x04, bit 5, can be used to reset the SMBus master mode. This bit should not be set if the DS100RT410 is in SMBus slave mode. This is an undefined condition.
When this bit is set, if the EN_SMB pin is floating (meaning that the DS100RT410 is in SMBus master mode), then the DS100RT410 will read the contents of the external EEPROM when the READ_EN pin is pulled low. This bit is not self-clearing, so it should be cleared after it is set.
When the DS100RT410 EN_SMB pin is floating (meaning that the DS100RT410 is in SMBus master mode), it will read from its external EEPROM when its READ_EN pin goes low. After the EEPROM read operation is complete, register 0x05, bit 4 will be set. Alternatively, the DS100RT410 will read from its external EEPROM when triggered by register 0x04, bit 4, as described below.
When register 0x04, bit 4, is set, the DS100RT410 reads its configuration from an external EEPROM over the SMBus immediately. When this bit is set, the DS100RT410 does not wait until the READ_EN pin is pulled low to read from the EEPROM. This EEPROM read occurs whether the DS100RT410 is in SMBus master mode or not. If the read from the EEPROM is not successful, for example because there is no EEPROM present, then the DS100RT410 may hang up and a power-up reset may be necessary to return it to proper operation. You should only set this bit if you know that the EEPROM is present and properly configured.
If the EEPROM read has already completed, then setting register 0x04, bit 4, will not have any effect. To cause the DS100RT410 to read from the EEPROM again it is necessary to set bit 5 of register 0x04, resetting the SMBus master mode. If the DS100RT410 is not in SMBus master mode, do not set this bit. After setting this bit, it should be cleared before further SMBus operations.
After SMBus master mode has been reset, the EEPROM read may be initiated either by pulling the READ_EN pin low or by then setting register 0x04, bit 4.
Register 0x05, bit 7, disables SMBus master mode. This prevents the DS100RT410 from trying to take command of the SMBus to read from the external EEPROM. Obviously this bit will have no effect if the EEPROM read has already taken place. It also has no effect if an EEPROM read is currently in progress. The only situations in which disabling EEPROM master mode read is valid are (1) when the DS100RT410 is in SMBus master mode, but the READ_EN pin has not yet gone low, and (2) when register 0x04, bit 5, has been used to reset SMBus master mode but the EEPROM read operation has not yet occurred.
Do not set this bit and bit 4 of register 0x04 simultaneously. This is an undefined condition and can cause the DS100RT410 to hang up.
Register 0x00, bit 2, and register 0x0a, bits 3:2
Bit 2 of channel register 0x00 are used to reset all the registers for the corresponding channel to their factory default settings. This bit is self-clearing. Writing this bit will clear any register changes you have made in the DS100RT410 since it was powered-up.
To reset just the CDR state machine without resetting the register values, which will re-initiate the lock and adaptation sequence for a particular channel, use channel register 0x0a. Set bit 3 of this register to enable the reset override, then set bit 2 to force the CDR state machine into reset. These bits can be set in the same operation. When bit 2 is subsequently cleared, the CDR state machine will resume normal operation. If a signal is present at the input to the selected channel, the DS100RT410 will attempt to lock to it and will adapt its CTLE according to the currently configured adapt mode for the selected channel. The adapt mode is configured by channel register 0x31, bits 6:5.
Control/Shared Register 0x05, bits 3:0, Register 0x01, bits 4 and 0, Register 0x30, bit 4, Register 0x32, and Register 0x36, bit 6
Each channel of the DS100RT410 will generate an interrupt under several different conditions. The DS100RT410 will always generate an interrupt when it loses CDR lock or when a signal is no longer detected at its input. If the HEO/VEO interrupt is enabled by setting bit 6 of register 0x36, then the retimer will generate an interrupt when the horizontal or vertical eye opening falls below the preset values even if the retimer remains locked. When one of these interrupt conditions occurs, the retimer alerts the system controller via hardware and provides additional details via register reads over the SMBus.
First, the open-drain interrupt line INT is pulled low. This indicates that one or more of the channels of the retimer has generated an interrupt. The interrupt lines from multiple retimers can be wire-ANDed together so that if any retimer generates an interrupt the system controller can be notified using a single interrupt input.
if the interrupt has occurred because the horizontal or vertical eye opening has dropped below the pre-set threshold, which is set in channel register 0x32, then bit 4 of register 0x30 will go high. This indicates that the source of the interrupt was the HEO or VEO.
If the interrupt has occurred because the CDR has fallen out of lock, or because the signal is no longer detected at the input, then bit 4 and/or bit 0 of register 0x01 will go high, indicating the cause of the interrupt.
In either case, the control/shared register set will indicate which channel caused the interrupt. This is read from bits 3:0 of control/shared register 0x05.
When an interrupt is detected by the controller on the interrupt input, the controller should take the following steps to determine the cause of the interrupt and clear it.
The channel registers referred to above, registers 0x01, 0x30, 0x32, and 0x36, are described in the channel registers table, Table 13.
Register 0x03, Register 0x13, bit 2, and Register 0x3a
To override the CTLE boost settings, register 0x03 is used. This register contains the currently-applied CTLE boost settings. The boost values can be overridden by using the two-bit fields in this register as listed in the table.
The final stage of the CTLE has an additional control bit which sets it to a limiting mode. For some channels, this additional setting improves the bit error rate performance. This bit is bit 2 of register 0x13.
If the DS100RT410 loses lock because of a change in the CTLE settings, the DS100RT410 will initiate its lock and adaptation sequence again. Thus, if you write new CTLE boost values to register 0x03 and 0x13 which cause the DS100RT410 to drop out of lock, the DS100RT410 may, in the process of reacquiring the CDR lock, reset the CTLE settings to different values than those you set in register 0x03 and 0x13. If this behavior is not understood, it can appear that the DS100RT410 did not accept the values you wrote to the CTLE boost registers. What's really happening, however, is that the lock and adaptation sequence is overriding the CTLE values you wrote to the CTLE boost registers. This will not happen unless the DS100RT410 drops out of lock.
If the adapt mode is set to 0 (bits 6:5 of channel register 0x31), then the CTLE boost values will not be overridden, but the DS100RT410 may still lose lock. If this happens, the DS100RT410 will attempt to reacquire lock. if the reference mode is set correctly, and if the rate/subrate code is set to permit it, the DS100RT410 will begin searching for CDR lock at the highest allowable VCO divider ratio – that is, at the lowest configured bit rate. At this lowest bit rate, the CTLE boost settings used will come not from the values in register 0x03, and 0x13, but rather from register 0x3a, the fixed CTLE boost setting for lower data rates. This setting will be written into boost setting register 0x03 during the lock search process. This value may be different from the value you set in register 0x03, so, again, it may appear that the DS100RT410 has not accepted the CTLE boost settings you set in registers 0x03 and 0x13. The interactions of the lock and adaptation sequences with the manually-set CTLE boost settings can be difficult to understand.
To manually override the CTLE boost under all conditions, perform the following steps.
If the DS100RT410 loses lock when the CTLE boost settings are set according to the sequence above, the DS100RT410 will try to reacquire lock, but it will not change the CTLE boost settings in order to do so.
Register 0x08, bits 4:0, Register 0x09, bit 7, Register 0x0b, bits 4:0, Register 0x36, bits 5:4, and Register 0x2f, bits 7:6 and 5:4
Registers 0x08 and 0x0b contain CAP DAC override values. Normally, when bits 5:4 of register 0x36 are set to 2'b11, then the DS100RT410 performs an initial search to determine the correct CAP DAC setting (coarse VCO tuning) for the selected rate and subrate. The rate and subrate settings (bits 7:6 and 5:4 of register 0x2f) determine the frequency range to be searched, with the 25 MHz reference clock used as the frequency reference for the frequency search.
The CAP DAC value can be overridden by writing new values to bits 4:0 of register 0x08 (for CAP DAC setting 1) and bits 4:0 of 0x0b (for CAP DAC setting 2). The override bit, bit 7 of register 0x09 must be set for the override CAP DAC values to take effect. Since the valid rate and subrate setting for 10 GbE and 1 GbE applies to multiple data rates, there are two CAP DAC values for this rate. The first is in register 0x08, bits 4:0, and the second is in register 0x0b, bits 4:0. The DS100RT410 will use the CAP DAC value in register 0x08 for the larger divide ratio (8) associated with the selected rate and subrate to try and acquire lock. If it fails to acquire lock, it will use the CAP DAC value in register 0x0b with the smaller divide ratio (higher VCO frequency) associated with the selected rate and subrate (1). It will continue to try to acquire lock in this way until it either succeeds or the override bit (bit 7 of register 0x09) is cleared.
Register 0x09, bit 5, Register 0x14, bits 7:6, and Register 0x1e, bits 7:5
By default, the DS100RT410 output for each channel will be as listed in Table 3.
|INPUT SIGNAL STATUS||CHANNEL STATUS||OUTPUT STATUS|
|Not Present||No Signal Detected||Muted|
This default behavior can be modified by register writes.
Register 0x1e, bits 7:5, contain the output multiplexer override value. The values of this three-bit field and the corresponding meanings of each are listed in Table 4.
|BIT FIELD VALUE||OUTPUT MULTIPLEXER SETTING||COMMENTS|
|0x7||Mute||Default when no signal is present or when the retimer is unlocked|
|0x5||10 MHz Clock||Internal 10 MHz clock
Clock frequency may not be precise
|0x4||PRBS Generator||PRBS Generator must be enabled to output PRBS sequence|
|0x3||VCO Q-Clock||Register 0x09, bit 4, and register 0x1e, bit 0, must be set to enable the VCO Q-Clock|
|0x1||Retimed Data||Default when the retimer is locked|
If the output multiplexer is not overridden, that is, if bit 5 of register 0x09 is not set, then the value in register 0x1e, bits 7:5, controls the output produced when the retimer has a signal at its input, but is not locked to it. The default value for this bit field, 0x7, causes the retimer output to mute when the retimer is not locked to an input signal. Writing a value of 0x0 to this bit field, for example, will cause the retimer to output raw data when it is not locked to its input signal.
Setting the override bit, bit 5 of register 0x09, will cause the retimer to output the value selected by the bit field in register 0x1e, bits 7:5, even when the retimer is locked.
When no signal is present at the input to the selected channel of the DS100RT410 the signal detect circuitry will power down the channel. This includes the output driver which is therefore muted when no signal is present at the input. If you want to get an output when no signal is present at the input, for example to enable a free-running PRBS sequence, the first step is to override the signal detect. In order to force the signal detect on, set bit 7 and clear bit 6 of channel register 0x14. Even if there is no signal at the input to the channel, the channel will be enabled. If the channel was disabled before, the current drain from the supply will increase by
100–150 mA depending upon the other channel settings in the device. This increased current drain indicates that the channel is now enabled.
The second step is to override the output multiplexer setting. This is accomplished by setting bit 5 of register 0x09, the output multiplexer override. Once this bit is set, the value of register 0x1e, bits 7:5 will control the output of the channel. Note that if either retimed or raw data is selected, the output will just be noise. The device output may saturate to a static 1 or 0.
If there is no signal, the VCO clock will be free-running. Its frequency will depend upon the divider and CAP DAC settings and it will vary from part to part and over temperature.
If the PRBS generator is enabled, the PRBS generator output can be selected. This can either be at a data rate determined by the free-running VCO or at a data rate determined by the input signal, if one is present. If a signal is present at the input and the DS100RT410 can lock to it, the output of the PRBS generator will be synchronous with the input signal, but the bit stream output will be determined by the PRBS generator selection.
The 10-MHz clock is always available at the output when the output multiplexer is overridden. The 10-MHz clock is a free-running oscillator in the DS100RT410 and is not synchronous to the input or to anything else in the system. The clock frequency will be approximately 10 MHz, but this will vary from part to part.
If there is a signal present at the input, it is not necessary to override the signal detect. Clearing bits 7 and 6 of register 0x14 will return control of the signal detect to the DS100RT410. Normally, when the retimer is locked to a signal at its input, it will output retimed data. However, if desired, the output multiplexer can be overridden in this condition to output raw data. It can also be set to output any of the other signals listed in Table 4. If there is an input signal, and if the DS100RT410 is locked to it, the VCO I-Clock, the VCO Q-Clock, and the output of the PRBS generator, if it is enabled, will be synchronous to the input signal.
When a signal is present at the input, it might be desired to output the raw data in order to see the effects of the CTLE without the CDR. It might also be desired to enable the PRBS generator and output this signal, replacing the data content of the input signal with the internally-generated PRBS sequence.
Register 0x09, bit 2, and Register 0x18, bits 6:4
In normal operation, the DS100RT410 sets its VCO divider to the correct divide ratio, either 1, 2, 4, 8, or 16, depending upon the bit rate of the signal at the channel input. It is possible to override the divider selection. This might be desired if the VCO is set to free-run, for example, to output a signal at a sub-harmonic of the actual VCO frequency.
In order to override the VCO divider settings, first set bit 2 of register 0x09. This is the VCO divider override enable. Once this bit is set, the VCO divider setting is controlled by the value in register 0x18, bits 6:4. The valid values for this three-bit field are 0x0 to 0x4. The mapping of the bit field values to the divider ratio is listed in Table 5.
|BIT FIELD VALUE||DIVIDER RATIO|
In normal operation, the DS100RT410 will determine the required VCO divider ratio automatically. The most common application for overriding the divider ratio is when the VCO is set to free-run. Normally the divider ratio should not be overridden except in this case.
Register 0x0d, bit 5, Register 0x1e, bit 4, and Register 0x30, bit 3 and bits 1:0
The DS100RT410 includes an internal PRBS generator which can generate standard PRBS-9 and PRBS-31 bit sequences. The PRBS generator can produce a PRBS sequence that is synchronous to the incoming data signal, or it can generate a PRBS sequence using the internal free-running VCO as a clock. Both modes of operation are described in the paragraphs that follow.
To produce a PRBS sequence that is synchronized to the incoming data signal, the DS100RT410 must be locked to the incoming signal. When this is true, the signal detect is set and the channel is active. In addition, the VCO is locked to the incoming signal The VCO will remain locked to the incoming signal regardless of the state of the output multiplexer.
To activate the PRBS generator, first set bit 4 of register 0x1e. This bit enables the PRBS generator digital circuitry. Then reset the PRBS clock by clearing bit 3 of register 0x30. Select either PRBS-9 or PRBS-31 by setting bits 1:0 of register 0x30. Set this bit field to 0x0 for PRBS-9 and to 0x2 for PRBS-31. Then load the PRBS clock by setting bit 3 of register 0x30. Finally, enable the PRBS clock by setting bit 5 of register 0x0d. This sequence of register writes will enable the internal PRBS generator.
As described above, to select the PRBS generator as the output for the selected channel, set bit 5 of register 0x09, the output multiplexer override. Then write 0x4 to bits 7:5 of register 0x1e. This selects the PRBS generator for output.
For the case described above, the output PRBS sequence will be synchronous to the incoming data. There are two other cases of interest. The first is when there is an input signal but the PRBS sequence should not be synchronous to it. In other words, in this case it is desired that the VCO should free-run. The second case is when there is no input signal, but the PRBS sequence should still be output. Again, in this case, the VCO is free-running.
The register settings for these two cases are almost the same. The only difference is that, if there is no input signal, then the channel will be disabled and powered-down by default. In order to force enable the channel, write a 1 to bit 7 and a 0 to bit 6 of register 0x14. This forces the signal detect to be active and enables the selected channel.
The remainder of the register write sequence is designed to disable the phase-locked loop so that the VCO can free run.
First write a 1 to bit 3 of register 0x09, then 0x0 to bits 1:0 of register 0x1b. This disables the charge pump for the phase-locked loop.
Next write a 1 to bit 2 of register 0x09. This enables the VCO divider override. Then set the VCO divider ratio by writing to register 0x18 as listed in Table 5. For an output frequency of approximately 10.3125 GHz, set the divider ratio to 1 by writing 0x0 to bits 6:4 of register 0x18. Do not clear bit 3 when you write a 1 to bit 2 of register 0x09.
Now write a 1 to bit 7 of register 0x09. This enables the VCO CAP DAC override. Write the desired VCO cap count to register 0x08, bits 4:0. The mapping of VCO frequencies to cap count will vary somewhat from part to part. The VCO cap count should be set to 0x0c to yield an output VCO frequency of approximately 10.3125 GHz. Do not clear bits 3 and 2 when you write a 1 to bit 7 of register 0x09.
Now write a 1 to bit 6 of register 0x09. This enables the VCO LPF DAC which can generate a VCO control voltage internally to the DS100RT410. Once the LPF DAC is enabled, write the desired value of the LPF DAC output in register 0x1f, bits 4:0. For an output VCO frequency of approximately 10.3125 GHz, set the LPF DAC setting to 0x12. Do not clear the remaining bits of register 0x09 when you write a 1 to bit 6.
Now, as above, enable the PRBS generator and set it to the desired bit sequence, then select the output to be the PRBS generator by setting the output multiplexer. Notice that when this entire sequence has been completed, bits 7:2 of register 0x09 will all be set. The default value of register 0x09 is 0x00, so you can clear all the overrides when you are ready to return to normal operation by writing 0x00 to register 0x09.
The VCO frequency in free-run will vary somewhat from part to part. In order to determine exact values of the CAP DAC and LPF DAC settings, it will be necessary to directly measure the VCO frequency using some sort of frequency-measurement device such as a frequency counter or a spectrum analyzer. When the VCO is set to free-run mode as above, you can select the VCO I-clock (in-phase clock) to be the output as listed in Table 4. You can measure the frequency of the VCO I-clock while adjusting the CAP DAC and LPF DAC values until the VCO I-clock frequency is acceptable for your application. Then you can once again select the PRBS generator as the output using the output multiplexer selection field.
Register 0x11, bits 7:6 and bit 5, Register 0x22, bit 7, Register 0x24, bit 7 and bit 0, Register 0x25, Register 0x26, Register 0x27, Register 0x28, and Register 0x2a
The DS100RT410 includes an internal eye opening monitor. The eye opening monitor is used by the retimer to compute a figure of merit for automatic adaptation of the CTLE. It can also be controlled and queried through the SMBus by a system controller.
The eye opening monitor produces error hit counts for settable phase and voltage offsets of the comparator in the retimer. This is similar to the way many Bit Error Rate Test Sets measure eye opening. At each phase and amplitude offset setting, the eye opening monitor determines the nominal bit value (“0” or “1”) using its primary comparator. This is the bit value that is resynchronized to the recovered clock and presented at the output of the DS100RT410. The eye opening monitor also determines the bit value detected by the offset comparator. This information yields an eye contour. Here's how this works.
If the offset comparator is offset in voltage by an amount larger than the vertical eye opening, for example, then the offset comparator will always decide that the current bit has a bit value of “0”. When the bit is really a “1”, as determined by the primary comparator, this is considered a bit error. The number of bit errors is counted for a settable interval at each setting of the offset phase and voltage of the offset comparator. These error counts can be read from registers 0x25 and 0x26 for sequential phase and voltage offsets. These error counts for each phase and voltage offsets form a 64 X 64 point array. A surface or contour plot of the error hit count versus phase and voltage offset produces an eye diagram, which can be plotted by external software.
The eye opening monitor works in two modes. In the first, only the horizontal and vertical eye openings are measured. The eye opening monitor first sweeps its variable-phase clock through one unit interval with the comparison voltage set to the mid point of the signal. This determines the midpoint of the horizontal eye opening. The eye opening monitor then sets its variable phase clock to the midpoint of the horizontal eye opening and sweeps its comparison voltage. These two measurements determine the horizontal and vertical eye openings. The horizontal eye opening value is read from register 0x27 and the vertical eye opening from register 0x28. Both values are single byte values.
The measurement of horizontal and vertical eye opening is very fast. The speed of this measurement makes it useful for determining the adaptation figure of merit. In normal operation, the HEO and VEO are automatically measured periodically to determine whether the DS100RT410 is still in lock. Reading registers 0x27 and 0x28 will yield the most-recently measured HEO and VEO values.
In normal operation, the eye monitor circuitry is powered down most of the time to save power. When the eye is to be measured under external control, it must first be enabled by writing a 0 to bit 5 of register 0x11. The default value of this bit is 1, which powers down the eye monitor except when it is powered-up periodically by the CDR state machine and used to test CDR lock. The eye monitor must be powered up to measure the eye under external SMBus control.
Bits 7:6 of register 0x11 are also used during eye monitor operation to set the EOM voltage range. This is described below. A single write to register 0x11 can set both bit 5 and bits 7:6 in one operation.
Register 0x3e, bit 7, enables horizontal and vertical eye opening measurements as part of the lock validation sequence. When this bit is set, the CDR state machine periodically uses the eye monitor circuitry to measure the horizontal and vertical eye opening. If the eye openings are too small, according to the pre-determined thresholds in register 0x6a, then the CDR state machine declares lock loss and begins the lock acquisition process again. For SMBus acquisition of the internal eye, this lock monitoring function must be disabled. Prior to overriding the EOM by writing a 1 to bit 0 of register 0x24, disable the lock monitoring function by writing a 0 to bit 7 of register 0x3e. Once the eye has been acquired, you can reinstate HEO and VEO lock monitoring by once again writing a 1 to bit 7 of register 0x3e.
Under external SMBus control, the eye opening monitor can be programmed to sweep through all its 64 states of phase and voltage offset autonomously. This mode is initiated by setting register 0x24, bit 7, the fast_eom mode bit. Register 0x22, bit 7, the eom_ov bit, should be cleared in this mode.
When the fast_eom bit is set, the eye opening monitor operation is initiated by setting bit 0 of register 0x24, which is self-clearing. As soon as this bit is set, the eye opening monitor begins to acquire eye data. The results of the eye opening monitor error counter are stored in register 0x25 and 0x26. In this mode the eye opening monitor results can be obtained by repeated multi-byte reads from register 0x25. It is not necessary to read from register 0x26 for a multi-byte read. As soon as the eight most significant bits are read from register 0x25, the eight least significant bits for the current setting are loaded into register 0x25 and they can be read immediately. As soon as the read of the eight most significant bits has been initiated, the DS100RT410 sets its phase and voltage offsets to the next setting and starts its error counter again. The result of this is that the data from the eye opening monitor is available as quickly as it can be read over the SMBus with no further register writes required. The external controller just reads the data from the DS100RT410 over the SMBus as fast as it can. When all the data has been read, the DS100RT410 clears the eom_start bit.
If multi-byte reads are not used, meaning that the device is addressed each time a byte is read from it, then it is necessary to read register 0x25 to get the MSB (the eight most significant bits) and register 0x26 to get the LSB (the eight least significant bits) of the current eye monitor measurement. Again, as soon as the read of the MSB has been initiated, the DS100RT410 sets its phase and voltage offsets to the next setting and starts its error counter again. In this mode both registers 0x25 and 0x26 must be read in order to get the eye monitor data. The eye monitor data for the next set of phase and voltage offsets will not be loaded into registers 0x25 and 0x26 until both registers have been read for the current set of phase and voltage offsets.
In all eye opening monitor modes, the amount of time during which the eye opening monitor accumulates eye opening data can be set by the value of register 0x2a. In general, the greater this value the longer the accumulation time. When this value is set to its maximum possible value of 0xff, the maximum number of samples acquired at each phase and amplitude offset is approximately 218. Even with this setting, the eye opening monitor values can be read from the SMBus with no delay. The eye opening monitor operation is sufficiently fast that the SMBus read operation cannot outrun it.
The eye opening is measured at the input to the data comparator. At this point in the data path, a significant amount of gain has been applied to the signal by the CTLE. In many cases, the vertical eye opening as measured by the EOM will be on the order of 400 to 500 mV peak-to-peak. The secondary comparator, which is used to measure the eye opening, has an adjustable voltage range from ±100 mV to ±400 mV. The EOM voltage range is normally set by the CDR state machine during lock and adaptation, but the range can be overridden by setting bit 6 to 0 of register 0x2C, so the voltage range can scale with the values in register 0x11, bits [7:6]. The values of this code and the corresponding EOM voltage ranges are listed in Table 6.
|VALUE in Bits 7:6 of REGISTER 0x11||EOM VOLTAGE RANGE (± mV)|
Note that the voltage ranges listed in Table 6 are the voltage ranges of the signal at the input to the data path comparator. These values are not directly equivalent to any observable voltage measurements at the input to the DS100RT410 . Note also that if the EOM voltage range is set too small the voltage sweep of the secondary comparator may not be sufficient to capture the vertical eye opening. When this happens the eye boundaries will be outside the vertical voltage range of the eye measurement.
Register 0x18, bit 2
Normally the rise and fall times of the output driver of the DS100RT410 are set by the slew rate of the output transistors. By default, the output transistors are biased to provide the maximum possible slew rate, and hence the minimum possible rise and fall times. In some applications, slower rise and fall times may be desired. For example, slower rise and fall times may reduce the amplitude of electromagnetic interference (EMI) produced by a system.
Setting bit 2 of register 0x18 will adjust the output driver circuitry to increase the rise and fall times of the signal. Setting this bit will approximately double the nominal rise and fall times of the DS100RT410 output driver. This bit is cleared by default.
Register 0x1f, bit 7
In some systems, the polarity of the data does not matter. In systems where it does matter, it is sometimes necessary, for the purposes of trace routing, for example, to invert the normal polarities of the data signals.
The DS100RT410 can invert the polarity of the data signals by means of a register write. Writing a 1 to bit 7 of register 0x1f inverts the polarity of the output signal for the selected channel. This can provide additional flexibility in system design and board layout.
Register 0x2c, bits 5:4, Register 0x31, bits 6:5, Register 0x6b, Register 0x6c, Register 0x6d, and Register 0x6e, bits 7 and 6
The default figure of merit for the CTLE is simple. The horizontal and vertical eye openings are measured for each CTLE boost setting. The vertical eye opening is scaled to a constant reference vertical eye opening and the smaller of the horizontal or vertical eye opening is taken as the figure of merit for that set of equalizer settings. The objective is to adapt the equalizer to a point where the horizontal and vertical eye openings are both as large as possible. This usually provides optimum bit error rate performance for most transmission channels.
In some systems the adaptation can reach a better setting if only the horizontal or vertical eye opening is used to compute the figure of merit rather than using both. This will be system-dependent and the user must determine through experiment whether this provides better adaptation in the user's system.
The CTLE figure of merit type is selected using the two-bit field in register 0x31, bits 6:5.
For some transmission media the adaptation can reach a better setting if a different figure of merit is used. The DS100RT410 includes the capability of adapting based on a configurable figure of merit. The configurable figure of merit is structured as listed in Equation 1.
In this equation, HEO is horizontal eye opening, VEO is vertical eye opening, FOM is the figure of merit, and the factors a, b, and c are set using registers 0x6b, 0x6c, and 0x6d respectively.
In order to use the configurable figure of merit, the enable bits must be set. To use the configurable figure of merit for the CTLE adaptation, set bit 7 of register 0x6e, the en_new_fom_ctle bit.
Register 0x2f, bits 7:6 and 5:4
The rate and subrate settings, which configure the set of VCO frequencies to which the VCO coarse tuning is to be calibrated are set using channel register 0x2f. Bits 7:6 are RATE<1:0>, and bits 5:4 are SUBRATE<1:0>.
Register 0x31, bits 6:5, and Register 0x33, bits 7:4 and 3:0, Register 0x34, bits 3:0, Register 0x35, bits 4:0, Register 0x3e, bit 7, and Register 0x6a
There are two adaptation modes available in the DS100RT410.
Bits 6:5 of register 0x31 determine the adaptation mode to be used. The mapping of these register bits to the adaptation algorithm is listed in Table 13.
|REGISTER 0X31, BIT 6
|REGISTER 0x31, BIT 5
|0||1||01||Adapt CTLE Until Optimum (Default)|
By default the DS100RT410 requires that the equalized internal eye exhibit horizontal and vertical eye openings greater than a pre-set minimum in order to declare a successful lock. The minimum values are set in register 0x6a.
The DS100RT410 continuously monitors the horizontal and vertical eye openings while it is in lock. If the eye opening falls below the threshold set in register 0x6a, the DS100RT410 will declare a loss of lock.
The continuous monitoring of the horizontal and vertical eye openings may be disabled by clearing bit 7 of register 0x3e.
Register 0x24, bit 2, and Register 0x2f, bit 0
When the DS100RT410 becomes unlocked, it will automatically try to acquire lock. If an adaptation mode is selected using bits 6:5 in register 0x31, the DS100RT410 will also try to adapt its CTLE.
Adaptation can also be initiated by the user. CTLE adaptation can be initiated by setting and then clearing register 0x2f, bit 0.
Register 0x36, bits 5:4
Register 0x36, bits 5:4, are the ref_mode<1:0> bits. These bits should be set to a value of 2'b11. Note that this is not the default. The reference mode must be set prior to using the DS100RT410.
A 25 MHz reference clock signal must be provided on the reference in pin (pin 19). The use of the reference clock in the DS100RT410 is explained below.
First, the reference clock allows the DS100RT410 to calibrate its VCO frequency at power-up and upon reset. This enables the DS100RT410 to determine the optimum coarse VCO tuning setting a-priori, which makes phase lock much faster. The DS100RT410 is not required to tune through the available coarse VCO tuning settings as it tries to acquire lock to an input signal. It can select the correct setting immediately.
Second, if the DS100RT410 loses lock for some reason and the VCO drifts from its phase-locked frequency, the DS1010DF410 can detect this very quickly using the reference clock. Detecting an out-of-lock condition quickly allows the DS100RT410 to raise an interrupt indicating that it has lost lock quickly, which the system controller can then service to correct the problem quickly.
Finally, some data signals with large jitter spurs in their frequency spectra can cause the DS1100DF410 to false lock. This occurs when the data pattern exhibits strong discrete frequency components in its frequency spectrum, or when the data pattern has a lot of periodic jitter imposed on it. If you look at such a signal in the frequency domain using a spectrum analyzer, it will clearly show “spurs” close in to the fundamental data rate frequency. These spurs can cause the DS100RT410 to false lock.
Using the 25 MHz reference clock, the DS100RT410 can detect when it is locked to a jitter spur. When this happens, the DS100RT410 will re-initiate the adaptation and lock sequence until it locks to the correct data rate. This provides immunity to false lock conditions.
The reference clock mode is set by a two-bit field, register 0x36, bits 5:4. This field should always be set to a value of 3 or 2'b11.
Register 0x2c, bits 3:0, Register 0x2f, bit 3, Register 0x39, bits 4:0, and Registers 0x50-0x5f
The CTLE adaptation algorithm operates by setting the CTLE boost stage controls to a set of pre-determined boost settings, each of which provides progressively more high-frequency boost. At each stage in the adaptation process, the DS100RT410 attempts to phase lock to the equalized signal. If the phase lock succeeds, the DS100RT410 measures the horizontal and vertical eye openings using the internal eye monitor circuit. The DS100RT410 computes a figure of merit for the eye opening and compares it to the previous best value of the figure of merit. While the figure of merit continues to improve, the DS100RT410 continues to try additional values of the CTLE boost setting until the figure of merit ceases to improve and begins to degrade. When the figure of merit starts to degrade, the DS100RT410 still continues to try additional CTLE settings for a pre-determined trial count called the “look-beyond” count, and if no improvement in the figure of merit results, it resets the CTLE boost values to those that produced the best figure of merit. The resulting CTLE boost values are then stored in register 0x03. The “look-beyond” count is configured by the value in register 0x2c, bits 3:0. The value is 0x2 by default.
The set of boost values used as candidate values during CTLE adaptation are stored as bit fields in registers 0x40-0x5f. The default values for these settings are listed in Table 8. These values may be overridden by setting the corresponding register values over the SMBus. If these values are overridden, then the next time the CTLE adaptation is performed the set of CTLE boost values stored in these registers will be used for the adaptation. Resetting the channel registers by setting bit 2 of channel register 0x00 will reset the CTLE boost settings to their defaults. So will power-cycling the DS100RT410.
(CTLE STAGE 0)
(CTLE STAGE 1)
(CTLE STAGE 2)
(CTLE STAGE 3)
As an alternative to, or in conjunction with, writing the CTLE boost setting registers 0x40 through 0x5f, it is possible to set the starting CTLE boost setting index. To override the default setting, which is 0, set bit 3 of register 0x2f. When this bit is set, the starting index for adaptation comes from register 0x39, bits 4:0. This is the index into the CTLE settings table in registers 0x40 through 0x5f. When this starting index is 0, which is the default, CTLE adaptation starts at the first setting in the table, the one in register 0x40, and continues until the optimum FOM is reached.
Register 0x2d, bits 2:0
There are eight levels of output differential voltage available in the DS100RT410, from 0.6 V to 1.3 V in 0.1 V increments. The values drv_sel_vod[2:0] in bits 2:0 of register 0x2d set the output VOD. The available VOD settings and the corresponding values of this bit field are listed in Table 9.
|BIT 2, DRV_SEL_VOD||BIT 1, DRV_SEL_VOD||BIT 0, DRV_SEL_VOD||SELECTED VOD (V, PEAK-TO-PEAK, DIFFERENTIAL)|
Register 0x15, bits 2:0 and bit 6
Fifteen output de-emphasis settings are available in the DS100RT410, ranging from 0 dB to -12 dB. The de-emphasis values come from register 0x15, bits 2:0, which make up the bit field dvr_dem<2:0>, and register 0x15, bit 6, which is the de-emphasis range bit.
The available driver de-emphasis settings and the mapping to these bits are listed in Table 10.
|REGISTER 0X15, BIT 2, DVR_DEM||REGISTER 0X15, BIT 1, DRV_DEM||REGISTER 15, BIT 0, DRV_DEM||REGISTER 0x15, BIT 6, DRV_DEM_RANGE||DE-EMPHASIS SETTING (dB)|
There are two types of device registers in the DS100RT410. These are the control/shared registers and the channel registers. The control/shared registers control or allow observation of settings which affect the operation of all channels of the DS100RT410. They are also used to select which channel of the device is to be the target channel for reads from and writes to the channel registers.
The channel registers are used to set all the configuration settings of the DS100RT410. They provide independent control for each channel of the DS100RT410 for all the settable device characteristics.
Any registers not described in the tables that follow should be treated as reserved. The user should not try to write new values to these registers. The user-accessible registers described in the tables that follow provide a complete capability for customizing the operation of the DS100RT410 on a channel-by-channel basis.
Many of the registers in the DS100RT410 are divided into bit fields. This allows a single register to serve multiple purposes, which may be unrelated.
Often configuring the DS100RT410 requires writing a bit field that makes up only part of a register value while leaving the remainder of the register value unchanged. The procedure for accomplishing this is to read in the current value of the register to be written, modify only the desired bits in this value, and write the modified value back to the register. Of course, if the entire register is to be changed, rather than just a bit field within the register, it is not necessary to read in the current value of the register first.
In all the register configuration procedures described in the following sections, this procedure should be kept in mind. In some cases, the entire register is to be modified. When only a part of the register is to be changed, however, the procedure described above should be used.
Any write operation targeting register 0xff writes to the control/shared register 0xff. This is the only register in the DS100RT410 with an address of 0xff.
Bit 2 of register 0xff is used to select either the control/shared register set or a channel register set. If bit 2 of register 0xff is cleared (written with a 0), then all subsequent read and write operations over the SMBus are directed to the control/shared register set. This situation persists until bit 2 of register 0xff is set (written with a 1).
There is a register with address 0x00 in the control/shared register set, and there is also a register with address 0x00 in each channel register set. If you read the value in register 0x00 when bit 2 of register 0xff is cleared to 0, then the value returned by the DS100RT410 is the value in register 0x00 of the control/shared register set. If you read the value in register 0x00 when bit 2 of register 0xff is set to 1, then the value returned by the DS100RT410 is the value in register 0x00 of the selected channel register set. The channel register set is selected by bits 1:0 of register 0xff.
If bit 3 of register 0xff is set to 1 and bit 2 of register 0xff is also set to 1, then any write operation to any register address will write all the channel register sets in the DS100RT410 simultaneously. This situation will persist until either bit 3 of register 0xff or bit 2 of register 0xff is cleared. Note that when you write to register 0xff, independent of the current settings in register 0xff, the write operation ALWAYS targets the control/shared register 0xff. This channel select register, register 0xff, is unique in this regard.
Table 11 shows the control/shared register set. Any register addresses or register bits in the control/shared register set not listed in this table should be considered reserved. In this table, the mode is either R for Read-Only, R/W for Read-Write, or R/W/SC for Read-Write-Self-Clearing. If you try to write to a Read-Only register, the DS100RT410 will ignore it.
Strapped 7-bit address is 0x18 + SMBus_Addr[3:0]
|4||1||R||N||Device_ID4||Device ID code|
|6||0||RWSC||N||RST_SMB_REGS||1: Resets share registers. Self-clearing.|
|5||0||RWSC||N||RST_SMB_MAS||1: Reset for SMBus Master Mode|
|4||0||RW||N||rc_eeprm_rd||1: Force EEPROM Configuration|
|5||7||0||RW||N||disab_eeprm_cfg||Disable Master Mode EEPROM Configuration|
|4||1||R||N||EEPROM_READ_DONE||This bit is set to 1 when read from EEPROM is done|
|3||0||R||N||int_ch0||Set on Channel 0 Interrupt|
|2||0||R||N||int_ch1||Set on Channel 1 Interrupt|
|1||0||R||N||int_ch2||Set on Channel 2 Interrupt|
|0||0||R||N||int_ch3||Set on Channel 3 Interrupt|
|3||0||RW||N||WRITE_ALL_CH||Selects All Channels for Register Write. See Table 3.|
|2||0||RW||N||EN_CH_SMB||Enable Register Write to One or all Channels and Register Read from One Channel.
See Table 3.
|1:0||0||RW||N||SEL_CH_SMB||Selects Target Channel for Register Reads and Writes. See Table 3.|
Register 0xff, bits 3:0
Register 0xff, as described in Table 11, selects the channel or channels for channel register reads and writes. It is worth describing the operation of this register again for clarity. If bit 3 of register 0xff is set, then any channel register write applies to all channels. Channel register read operations always target only the channel specified in bits 1:0 of register 0xff regardless of the state of bit 3 of register 0xff. Read and write operations target the channel register sets only when bit 2 of register 0xff is set.
Bit 2 of register 0xff is the universal channel register enable. This bit must be set in order for any channel register reads and writes to occur. If this bit is set, then read operations from or write operations to register 0x00, for example, target channel register 0x00 for the selected channel rather than the control/shared register 0x00. In order to access the control/shared registers again, bit 2 of register 0xff should be cleared. Then the control/shared registers can again be accessed using the SMBus. Write operations to register 0xff always target the register with address 0xff in the control/shared register set. There is no other register, and specifically, no channel register, with address 0xff.
The contents of the channel select register, register 0xff, cannot be read back over the SMBus. Read operations on this register will always yield an invalid result. All eight bits of this register should always be set to the desired values whenever this register is written. Always write 0x0 to the four MSBs of register 0xff. The register set target selected by each valid value written to the channel select register is listed in Table 12.
|TARGETED CHANNEL SELECTION||COMMENTS|
|0x00||Shared||N/A||N/A||All reads and writes target shared register set|
|0x04||Channel||No||0||All reads and writes target channel 0 register set|
|0x05||Channel||No||1||All reads and writes target channel 1 register set|
|0x06||Channel||No||2||All reads and writes target channel 2 register set|
|0x07||Channel||No||3||All reads and writes target channel 3 register set|
|0x0c||Channel||Yes||0||All writes target all channel register sets, all reads target channel 0 register set|
|0x0d||Channel||Yes||1||All writes target all channel register sets, all reads target channel 1 register set|
|0x0e||Channel||Yes||2||All writes target all channel register sets, all reads target channel 2 register set|
|0x0f||Channel||Yes||3||All writes target all channel register sets, all reads target channel 3 register set|
Each of the four channels has a complete set of channel registers associated with it. The channel registers or the control/shared registers are selected by channel select register 0xff. The settings in this register control the target for subsequent register reads and writes until the contents of register 0xff are explicitly changed by a register write to register 0xff. As noted, there is only one register with an address of 0xff, the channel select register.
|BITS||DEFAULT VALUE (HEX)||MODE||EEPROM||FIELD NAME||DESCRIPTION|
|3||0||RW||N||RST_CORE||1: Reset core state machine
0: Normal Operation
|2||0||RW||N||RST_REGS||1: Resets channel registers, restores default values
0: Normal Operation
|1||0||RW||N||RST_REFCLK||1: Reset reference clock domain
0: Normal Operation
|0||0||RW||N||RST_VCO||1: Reset VCO DIV clock domain
0: Normal Operation
|4||0||R||N||CDR_LOCK_LOSS_INT||1: indicates loss of CDR lock after having acquired it.
Bit clears on read.
|0||0||R||N||SIG_DET_LOSS_INT||Loss of signal indicator.
Bit is set once signal is acquired and then lost.
|2||7:0||0x0||R||N||cdr_status||CDR Status [7:0]
Bit = PPM Count met
Bit = Auto Adapt Complete
Bit = Fail Lock Check
Bit = Lock
Bit = CDR Lock
Bit = Single Bit Limit Reached
Bit = Comp LPF High
Bit = Comp LPF Low
|3||7||0||RW||Y||EQ_BST0||This register can be used to force an EQ boost setting if used in conjunction with channel register 0x2D.|
|4||0||RW||Y||CDR_CAP_DAC_START4||Starting VCO Cap Dac Setting 0|
|3||0||RW||Y||CDR_CAP_DAC_START3||Starting VCO Cap Dac Setting 0|
|2||0||RW||Y||CDR_CAP_DAC_START2||Starting VCO Cap Dac Setting 0|
|1||0||RW||Y||CDR_CAP_DAC_START1||Starting VCO Cap Dac Setting 0|
|0||0||RW||Y||CDR_CAP_DAC_START0||Starting VCO Cap Dac Setting 0|
|9||7||0||RW||Y||DIVSEL_VCO_CAP_OV||Enable bit to override cap_cnt with value in register 0x0B[4:0]|
|6||0||RW||Y||SET_CP_LVL_LPF_OV||Enable bit to override lpf_dac_val with value in register 0x1F[4:0]|
|5||0||RW||Y||BYPASS_PFD_OV||Enable bit to override sel_retimed_loopthru and sel_raw_loopthru with values in reg 0x1E[7:5]|
|4||0||RW||Y||EN_FD_PD_VCO_PDIQ_OV||Enable bit to override en_fd, pd_pd, pd_vco, pd_pdiq with reg 0x1E, reg 0x1E, reg 0x1C, reg 0x1C|
|3||0||RW||Y||EN_PD_CP_OV||Enable bit to override pd_fd_cp and pd_pd_cp with value in reg 0x1B[1:0]|
|2||0||RW||Y||DIVSEL_OV||Enable bit to override divsel with value in reg 0x18[6:4]
1: Override enable
0: Normal operation
|1||0||RW||Y||EN_FLD_OV||Enable to override pd_fld with value in reg 0x1E|
|0||0||RW||Y||PFD_LOCK_MODE_SM||Enable FD in lock state|
|A||7||0||RW||Y||SBT_EN||Enable bit to override sbt_en with value in reg 0x1D|
|Enable bit to overridephase detector charge pump settings with reg 0x1C[7:5]
Enable bit to override frequency detector charge pump settings with reg 0x1C[4:2]
|Enable bit to override loop filter comparator trip voltage with reg 0x16[7:0]|
|4||1||RW||Y||EN150_LPF_OV||Enable bit to override en150_lpf with value in reg 0x1F|
|3||0||RW||N||CDR_RESET_OV||Enable bit to override CDR reset with reg 0x0A|
|2||0||RW||N||CDR_RESET_SM||1: CDR is put into reset
0: normal CDR operation
|1||0||RW||N||CDR_LOCK_OV||Enable CDR lock signal override with reg 0x0A|
|0||0||RW||N||CDR_LOCK||CDR lock signal override bit|
|4||0||RW||Y||CAP_DAC_START1||Starting VCO cap dac setting 1|
|3||1||RW||Y||CAP_DAC_START1||Starting VCO cap dac setting 1|
|2||1||RW||Y||CAP_DAC_START1||Starting VCO cap dac setting 1|
|1||1||RW||Y||CAP_DAC_START1||Starting VCO cap dac setting 1|
|0||1||RW||Y||CAP_DAC_START1||Starting VCO cap dac setting 1|
|3||1||RW||Y||SINGLE_BIT_LIMIT_CHECK_ON||1: Normal operation, device checks for single bit transitions as a gate to achieving CDR lock|
|5||0||RW||Y||PRBS_PATT_SHIFT_EN||PRBS Generator Clock Enable
|11||7||0||RW||Y||EOM_SEL_VRANGE||Manually set the EOM vertical range, used with channel register 0x2C:
00: ±100 mV
01: ±200 mV
10: ±300 mV
11: ±400 mV
|5||1||RW||Y||EOM_PD||1: Normal operation|
|4||1||RW||Y||EQ_EN_DC_OFF||1: Normal operation|
|2||0||RW||Y||EQ_LIMIT_EN||1: Configures the final stage of the equalizer to be a limiting stage.
0: Normal operation, final stage of the equalizer is configured to be a linear stage.
|14||7||0||RW||Y||EQ_SD_PRESET||1: Forces signal detect HIGH, and force enables the channel. Should not be set if bit 6 is set.
0: Normal Operation.
|6||0||RW||Y||EQ_SD_RESET||1: Forces signal detect LOW and force disables the channel. Should not be set if bit 7 is set.
0: Normal Operation.
|5||0||RW||Y||EQ_REFA_SEL1||Controls the signal detect assert levels.|
|3||0||RW||Y||EQ_REFD_SEL1||Controls the signal detect de-assert levels.|
|6||0||RW||Y||drv_dem_range||Driver De-emphasis Range|
|3||0||RW||N||DRV_PD||1: Powers down the high speed driver
0: Normal operation
|2||0||RW||Y||DRV_DEM2||Driver De-emphasis Setting[2:0]|
|6||1||RW||Y||PDIQ_SEL_DIV2||These bits will force the divider setting if 0x09 is set.
000: Divide by 1
001: Divide by 2
010: Divide by 4
011: Divide by 8
100: Divide by 16
All other values are reserved.
|1||1||RW||Y||CP_EN_CP_PD||1: Normal operation (phase detector charge pump enabled)|
|0||1||RW||Y||CP_EN_CP_FD||1: Normal operation (frequency detector charge pump enabled)|
|1C||7||0||RW||Y||EN_IDAC_PD_CP2||Phase detector charge pump setting. MSB located in channel register 0x0C. Override bit required for these bits to take effect|
|4||0||RW||Y||EN_IDAC_FD_CP2||Frequency detector charge pump setting. MSB located in channel register 0x0C. Override bit required for these bits to take effect|
|1D||7||0||RW||Y||SBT_EN||SBT enable override
0: Normal operation
|1E||7||1||RW||Y||PFD_SEL_DATA_MUX2||For these values to take effect, register 0x09 must be set to 1.
000: Raw Data*
001: Retimed Data
100: Pattern Generator
All other values are reserved.
|4||0||RW||N||PRBS_EN||1: Enable PRBS Generator|
|2||0||RW||Y||PFD_PD_PD||PFD phase detector power down override|
|1||0||RW||Y||PFD_EN_FLD||PFD enable FLD override|
|0||1||RW||Y||PFD_EN_FD||PFD enable frequency detector override|
|1F||7||0||RW||Y||Drv_sel_inv||Select Output Polarity Inverted|
|6||0||RW||Y||LPF_EN_150||When reg_0A=1, this bit will change the loop filter resistance.
1: 1500 Ω
0: 750 Ω
|22||7||0||RW||N||EOM_OV||1: Override enable for EOM manual control
0: Normal operation
|6||0||RW||N||EOM_SEL_RATE_OV||1: Override enable for EOMrate selection
0: Normal operation
|23||7||0||RW||N||EOM_GET_HEO_VEO_OV||1: Override enable for manual control of the HEO/VEO trigger
0: Normal operation
|24||7||0||RW||N||FAST_EOM||1: Enables fast EOM mode for fully eye capture. In this mode the phase DAC and voltage DAC of the EOM are automatically incremented through a 64 x 64 matrix. Values for each point are stored in channel registers 25 and 26.|
|5||0||RW||N||GET_HEO_VEO_ERROR_NO_HITS||GET_HEO_VEO sees no hits at zero crossing|
|4||0||RW||N||GET_HEO_VEO_ERROR_NO_OPENING||GET_HEO_VEO cannot see a vertical eye opening|
|1||0||RW||N||EOM_GET_HEO_VEO||1: Manually triggers a HEO/VEO measurement. Must be enabled with channel register 0x23.|
|0||0||RW||N||EOM_START||1: Starts EOM counter, self clearing|
|25||7||0||R||N||EOM_COUNT15||MSBs of EOM counter|
|26||7||0||R||N||EOM_COUNT7||LSBs of EOM counter|
|27||7||0||R||N||HEO7||HEO value, requires CDR to be locked for valid measurement|
|28||7||0||R||N||VEO7||VEO value, requires CDR to be locked for valid measurement|
|6||0||R||N||EOM_VRANGE_SETTING1||Use these bits to read back the EOM voltage range setting:
00: ±100 mV
01: ±200 mV
10: ±300 mV
11: ±400 mV
|2A||7||0||RW||Y||EOM_TIMER_THR7||Controls the amount of time the EOM samples each point in the eye for. The total counter bit width is 16-bits. This register is the upper 8-bits. The counter counts in 32-bit words. Therefore, the total number of bits is 32 times this value|
|3||0||RW||Y||EOM_MIN_REQ_HITS3||These bits set the number of hits for a particular phase and voltage location in the EOM before the EOM will indicate a hit has occurred. This filtering only affects the HEO measurement. Filter threshold ranges from 0 to 15 hits.|
|6||1||RW||Y||VEO_SCALE||Scale VEO based on EOM vrange|
|3||0||RW||Y||EQ_BST_OV||Allow override control of the EQ setting by writing to channel register 0x03. Not recommended for normal operation.|
|2||0||RW||Y||DRV_SEL_VOD2||Controls the VOD levels of the high speed drivers|
|3||0||RW||Y||INDEX_OV||If this bit is set to 1, reg 0x13 is to be used as a 5 bit index to the [31:0] array of EQ settings.|
|2||1||RW||Y||EN_PPM_CHECK||1: PPM check to be used as a qualifier when performing lock detect|
|1||1||RW||Y||EN_FLD_CHECK||For default ref_mode 3
0: FLD is enabled
1: FLD is disabled
|0||0||RWSC||N||CTLE_ADAPT||Starts CTLE adaption, self-clearing|
|4||0||R||N||HEO_VEO_INTERRUPT||Requires that channel register 0x36 be set.
1: Indicates that HEO/VEO dropped below the limits set in channel register 0x76 This bit is cleared after reading. This bit will stay set until it has been cleared by reading.
|3||0||RW||Y||PRBS_EN_DIG_CLK||This bit enables the clock to operate the PRBS generator and/or the PRBS checker. Toggling this bit is the primary method to reset the PRBS pattern generator and PRBS checker.|
|1||0||RW||Y||PRBS_PATTERN_SEL1||Selects the PRBS generator pattern to output. Requires that the pattern generator be configured properly.
|6||0||RW||Y||ADAPT_MODE1||00: no adaption
01: adapt CTLE only
|4||0||RW||Y||EQ_SM_FOM1||00: not valid
01: SM uses HEO only
10: SM uses VEO only
11: SM uses both HEO and VEO
|32||7||0||RW||Y||HEO_INT_THRESH3||These bits set the threshold for the HEO and VEo interrupt. Each threshold bit represents 8 counts of HEO or VEO.|
|33||7||1||RW||Y||HEO_THRESH3||Reserved for future use.|
|34||7||0||RW||N||PPM_ERR_RDY||1: Indicates that a PPM error count is read to be read from channel register 0x3B and 0x3C|
|6||0||RW||Y||LOW_POWER_MODE_DISABLE||By default, all blocks (except signal detect) power down after 100ms after signal detect goes low.|
|5||1||RW||Y||LOCK_COUNTER1||After achieving lock, the CDR continues to monitor the lock criteria. If the lock criteria fail, the lock is checked for a total of N number of times before declaring an out of lock condition, where N is set by this the value in these registers, with a max value of +3, for a total of 4. If during the N lock checks, lock is regained, then the lock condition is left HI, and the counter is reset back to zero.|
|35||7||0||RW||Y||DATA_LOCK_PPM1||Modifies the value of the ppm delta tolerance from channel register 0x64:
00 - ppm_delta[7:0] =1 x ppm_delta[7:0]
01 - ppm_delta[7:0] =1 x ppm_delta[7:0] + ppm_delta[3:1]
10 - ppm_delta[7:0] =2 x ppm_delta[7:0]
11 - ppm_delta[7:0] =2 x ppm_delta[7:0] + ppm_delta[3:1]
|5||0||RW||N||GET_PPM_ERROR||Get ppm error from ppm_count - clears when done. Normally updates continuously, but can be manually triggered with read value from channel register 0x3B and 0x3C|
|6||0||RW||Y||HEO_VEO_INT_EN||1: Enable HEO/VEO interrupt capability|
|5||1||RW||Y||REF_MODE1||11: Fast_lock all cap dac ref clock enabled (recommended)
10: constrained cap dac, ref clock enabled
01: referenceless constained cap dac
00: referenceless all cap dac
|2||0||RW||Y||CDR_CAP_DAC_RNG_OV||Over-ride enable for Cap DAC range|
|1||0||RW||Y||cdr_cap_dac_rng||Sets the stop value based on start value - (rng+1):
11:stop = start - 4
10: stop = start - 3
01: stop = start - 2
00: stop = start - 1
|37||7||0||R||N||CTLE_STATUS7||Feature is reserved for future use|
|6||0||RW||Y||EOM_RATE1||With eom_ov=1, these bits control the Eye Monitor Rate:
11: Use for Full Rate, Fastest
10 : Use for 1/2 Rate
01: Use for 1/4 Rate
00: Use for 1/8 Rate, Slowest
|4||0||RW||Y||START_INDEX4||Start index for EQ adaptation|
|3A||7||1||RW||Y||FIXED_EQ_BST0||During adaptation, if the divider setting is >2, then a fixed EQ setting from this register will be used. However, if channel register 0x6F is enabled, then an EQ adaptation will be performed instead|
|3E||7||1||RW||Y||HEO_VEO_LOCKMON_EN||Enable HEO/VEO lock monitoring.|
|40-5F||CTLE Settings for adaption – see Table 10|
|60||7||0||RW||Y||GRP0_OV_CNT7||Group 0 count LSB|
|61||7||0||RW||Y||CNT_DLTA_OV_0||Override enable for group 0 manual data rate selection|
|6||0||RW||Y||GRP0_OV_CNT14||Group 0 count MSB|
|62||7||0||RW||Y||GRP1_OV_CNT7||Group 1 count LSB|
|63||7||0||RW||Y||CNT_DLTA_OV_1||Override enable for group 1 manual data rate selection|
|6||0||RW||Y||GRP1_OV_CNT14||Group 1 count MSB|
|64||7||0||RW||Y||GRP0_OV_DLTA3||Sets the PPM delta tolerance for the PPM counter lock check for group 0. Must also program channel register 0x67.|
|3||0||RW||Y||GRP1_OV_DLTA3||Sets the PPM delta tolerance for the PPM counter lock check for group 1. Must also program channel register 0x67.|
|4||0||RW||N||CTLE_ADPT_FRC_EN||This feature is reserved for future use.|
|6A||7||0||RW||Y||VEO_LCK_THRSH3||VEO threshold to meet before lock is established. The LSB step size is 4 counts of VEO.|
|3||0||RW||Y||HEO_LCK_THRSH3||HEO threshold to meet before lock is established. The LSB step size is 4 counts of VEO.|
|6B||7||0||RW||Y||FOM_A7||Alternate Figure of Merit variable A. Max value for this register is 128, do not use the MSB|
|6C||7||0||RW||Y||FOM_B7||HEO adjustment for Alternate FoM, variable B|
|6D||7||0||RW||Y||FOM_C7||VEO adjustment for Alternate FoM, variable C|
|6E||7||0||RW||Y||EN_NEW_FOM_CTLE||1: CTLE adaption state machine will use the alternate FoM
HEO_ALT = (HEO-B)*A*2
VEO_ALT = (VEO-C)*(1-A)*2
The values of A,B,C are set in channel register 0x6B, 0x6C, and 0x6D. The value of A is equal to the register value divided by 128.
The Alternate FoM = (HEOB)* A*2 + (VEO-C)*(1-A)*2
|0||0||RW||N||GET_HV_ST_FRC_EN||This feature is reserved for future use.|
|2||0||RW||Y||EQ_LB_CNT2||CTLE look beyond count for adaption|