SNLS448A January 2013 – October 2015 DS100RT410
Figure 9 depicts an example power connections diagram for the DS100RT410. The supply (VDD) and ground (GND) Pins should be connected to power planes routed on adjacent layers of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply with distributed capacitance. Second, careful attention to supply bypassing through the proper use of bypass capacitors is required. A 0.1-μF bypass capacitor should be connected to each VDD Pin such that the capacitor is placed as close as possible to the DS100RT410. Smaller body size capacitors can help facilitate proper component placement. Additionally, capacitor with capacitance in the range of 1 μF to 10 μF should be incorporated in the power supply bypassing design as well. These capacitors can be either tantalum or an ultra-low ESR ceramic.