JAJSHS2 August   2019 DS160PR410

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 DC Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
        3. 7.5.1.3 SMBus/I2C Master Mode Configuration (EEPROM Self Load)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIE x4 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DisplayPort Application
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 SMBUS/I2C Timing Charateristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Slave Mode
TSDA-HD Data hold time 0.75 ns
TSDA-SU Data setup time 100 ns
TSDA-R SDA rise time, read operation Pull-up resistor = 1 kΩ, Cb = 50pF 150 ns
TSDA-F SDA fall time, read operation Pull-up resistor = 1 kΩ, Cb = 50pF 4.5 ns
Master Mode
fSCL SCL clock frequency EN_SMB = L3 (Master Mode) 260 303 346 kHz
TSCL-LOW SCL low period 1.66 1.90 2.21 µs
TSCL-HIGH SCL high period 1.22 1.40 1.63 µs
THD-START Hold time start operation 0.6 µs
TSU-START Setup time start operation 0.6 µs
TSDA-HD Data hold time 0.9 µs
TSDA-SU Data setup time 0.1 µs
TSU-STOP Stop condition setup time 0.6 µs
TBUF Bus free time between Stop-Start 1.3 µs
TSDC-R SCL rise time Pull-up resistor = 1 kΩ 300 ns
TSDC-F SCL fall time Pull-up resistor = 1 kΩ 300 ns
EEPROM Timing
TEEPROM EEPROM configuration load time Time to assert ALL_DONE_N after READ_EN_N has been asserted. Single device reading its configuration from an EEPROM with common channel configuration. This time scales with the number of devices reading from the same EEPROM. Does not include power-on reset time. 4 ms
TEEPROM EEPROM configuration load time Time to assert ALL_DONE_N after READ_EN_N has been asserted. Single device reading its configuration from an EEPROM. Non-common channel configuration. This time scales with the number of devices reading from the same EEPROM. Does not include power-on reset time. 7 ms
TPOR Power-on reset assertion time Internal power-on reset (PoR) stretch between stable power supply and de-assertion of internal PoR. The SMBus address is latched on the completion of the PoR stretch, and SMBus accesses are permitted once PoR completes. 30 ms