SNLS685 December   2020 DS160PR412

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x8 Lane Switching
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Pin-to-pin Passive versus Redriver Option
        4. 8.2.1.4 Application Curves
      2. 8.2.2 DisplayPort Application
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Application Curves

The DS160PR412 is a linear redriver that can be used to extend channel reach of a PCIe link. Normally, PCIe-compliant TX and RX are equipt with signal-conditioning functions and can handle channel losses of up to 28 dB at 8 GHz. In real implementation the channel reach is often lower. With the DS160PR412 in the link, the total channel loss between a PCIe root complex and an end-point can be extended up to 42 dB at 8 GHz.

Figure 8-3 shows an electric link that models a single channel of a PCIe link and eye diagrams measured at different locations along the link. The source that models a PCIe Transmitter sends a 16 Gbps PRBS-15 signal with P7 presets. After a transmission channel with –30 dB at 8 GHz insertion loss, the eye diagram is fully closed. The DS160PR412 with its CTLE set to the maximum (17 dB boost) together with the source TX equalization compensates for the losses of the pre-channel (TL1) and opens the eye at the output of the device.

The post-channel (TL2) losses mandate the use of PCIe RX equalization functions such as CTLE and DFE that are normally available in a PCIe-compliant receiver.

GUID-20201221-CA0I-4CZS-WCHM-PSQJV0TNJFXZ-low.gif Figure 8-3 PCIe 4.0 Link Reach Extension Using the DS160PR412