JAJS707E January   2001  – January 2018 DS92LV040A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略機能図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Circuits and Timing Waveforms
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Multipoint Communications
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Supply Voltage
        2. 9.2.3.2 Supply Bypass Capacitance
        3. 9.2.3.3 Termination Resistors
        4. 9.2.3.4 Interconnecting Media
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Microstrip vs. Stripline Topologies
      2. 11.1.2 Dielectric Type and Board Construction
      3. 11.1.3 Recommended Stack Layout
      4. 11.1.4 Separation Between Traces
      5. 11.1.5 Crosstalk and Ground Bounce Minimization
      6. 11.1.6 Decoupling
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 AC Electrical Characteristics

Over recommended operating supply voltage and temperature ranges unless otherwise specified.(1)
PARAMETERTEST CONDITIONS(2)MINTYPMAXUNIT
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
tPHLD Differential Prop. Delay High to Low(3) RL = 27Ω,
Figure 2, Figure 3,
CL = 10 pF		 1 1.5 2.3 ns
tPLHD Differential Prop. Delay Low to High(3) 1 1.5 2.3 ns
tSKD1 Differential Skew |tPHLD–tPLHD| (duty cycle)(4)(3) 80 160 ps
tCCSK Channel to Channel Skew (all 4 channels)(3)(5) 220 400 ps
tTLH Transition Time Low to High (20% to 80%) 0.4 0.75 1.3 ns
tTHL Transition Time High to Low (80% to 20%) 0.4 0.75 1.3 ns
tPHZ Disable Time High to Z RL = 27Ω,
Figure 4, Figure 5,
CL = 10 pF		 5 10 ns
tPLZ Disable Time Low to Z 5 10 ns
tPZH Enable Time Z to High 5 10 ns
tPZL Enable Time Z to Low 5 10 ns
fMAXD Ensured operation per data sheet up to the Min. Duty Cycle 45/55%,Transition time ≤ 25% of period(3) 85 125 MHz
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
tPHLDR Differential Prop. Delay High to Low(3) Figure 6, Figure 7,
CL = 15 pF		 1.6 2.4 3.2 ns
tPLHDR Differential Prop Delay Low to High(3) 1.6 2.4 3.2 ns
tSDK1R Differential Skew |tPHLD–tPLHD| (duty cycle)(4)(3) 85 160 ps
tCCSKR Channel to Channel Skew (all 4 channels)(3)(5) 140 300 ps
tTLHR Transition Time Low to High (10% to 90%)(3) 0.85 1.25 2 ns
tTHLR Transition Time High to Low (90% to 10%)(3) 0.85 1.03 2 ns
tPHZ Disable Time High to Z RL = 500Ω,
Figure 8, Figure 9,
CL = 15 pF		 3 10 ns
tPLZ Disable Time Low to Z 3 10 ns
tPZH Enable Time Z to High 3 10 ns
tPZL Enable Time Z to Low 3 10 ns
fMAXR Ensured operation per data sheet up to the Min. Duty Cycle 45/55%,Transition time ≤ 25% of period(3) 85 125 MHz
(1) Generator waveforms for all tests unless otherwise specified: f = 25 MHz, ZO = 50 Ω, tr, tf = <1 ns (0%–100%). To ensure fastest propagation delay and minimum skew, data input edge rates should be equal to or faster than 1 ns/V; control signals equal to or faster than 3ns/V. In general, the faster the input edge rate, the better the AC performance.
(2) CL includes probe and fixture capacitance.
(3) Propagation delays, transition times, and receiver threshold are ensured by design and characterization.
(4) tSKD1 |tPHLD–tPLHD| is the worst case pulse skew (measure of duty cycle) over recommended operation conditions.
(5) Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge.