JAJSDR5A August   2017  – January 2018 INA828

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      INA828の簡略化された内部回路図
      2.      入力オフセット電圧ドリフトの代表的な分布
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Setting the Gain
        1. 7.3.1.1 Gain Drift
      2. 7.3.2 EMI Rejection
        1. Table 2. INA828 EMIRR for Frequencies of Interest
      3. 7.3.3 Input Common-Mode Range
      4. 7.3.4 Input Protection
      5. 7.3.5 Operating Voltage
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Reference Terminal
    2. 8.2 Input Bias Current Return Path
    3. 8.3 PCB Assembly Effects on Precision
    4. 8.4 Typical Application
      1. 8.4.1 Design Requirements
      2. 8.4.2 Detailed Design Procedure
      3. 8.4.3 Application Curves
    5. 8.5 Other Application Examples
      1. 8.5.1 Resistance Temperature Detector Interface
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VOSI Input stage offset voltage(1)(3) G = 100, RTI 20 50 µV
TA = –40°C to +125°C(2) 90 µV
vs temperature, TA = –40°C to +125°C 0.5 µV/°C
VOSO Output stage offset voltage(1)(3) G = 1, RTI 50 250 µV
TA = –40°C to +125°C(2) 500 µV
vs temperature, TA = –40°C to +125°C 5 µV/°C
PSRR Power-supply rejection ratio G = 1, RTI 110 120 dB
G = 10, RTI 114 130
G = 100, RTI 130 135
G = 1000, RTI 136 140
zid Differential impedance 100 || 1 GΩ || pF
zic Common-mode impedance 100 || 10 GΩ || pF
RFI filter, –3-dB frequency 53 MHz
VCM Operating input range(4) (V–) + 2 (V+) – 2 V
VS = ±2.25 V to ±18 V, TA = –40°C to +125°C See Figure 48 to Figure 51
Input overvoltage range TA = –40°C to +125°C ±40 V
CMRR Common-mode rejection ratio At dc to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
G = 1		 90 100 dB
At dc to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
G = 10		 110 120
At dc to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
G = 100		 130 140
At dc to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
G = 1000		 140 145
BIAS CURRENT
IB Input bias current VCM = VS / 2 0.15 0.6 nA
TA = –40°C to +125°C 2
IOS Input offset current VCM = VS / 2 0.15 0.6 nA
TA = –40°C to +125°C 2
NOISE VOLTAGE
eNI Input stage voltage noise(6) f = 1 kHz, G = 100, RS = 0 Ω 7 nV/√Hz
fB = 0.1 Hz to 10 Hz, G = 100, RS = 0 Ω 0.14 µVPP
eNO Output stage voltage noise(6) f = 1 kHz, RS = 0 Ω 90 nV/√Hz
fB = 0.1 Hz to 10 Hz, RS = 0 Ω 7.7 µVPP
In Noise current f = 1 kHz 170 fA/√Hz
fB = 0.1 Hz to 10 Hz, G = 100 4.7 pAPP
GAIN
G Gain equation 1 + (50 kΩ / RG) V/V
Range of gain 1 1000 V/V
GE Gain error G = 1, VO = ±10 V ±0.005% ±0.025%
G = 10, VO = ±10 V ±0.025% ±0.15%
G = 100, VO = ±10 V ±0.025% ±0.15%
G = 1000, VO = ±10 V ±0.05%
Gain vs temperature(5) G = 1, TA = –40°C to +125°C ±5 ppm/°C
G > 1, TA = –40°C to +125°C ±50
Gain nonlinearity G = 1 to 10, VO = –10 V to +10 V, RL = 10 kΩ 1 10 ppm
G = 100, VO = –10 V to +10 V, RL = 10 kΩ 15
G = 1000, VO = –10 V to +10 V, RL = 10 kΩ 20
G = 1 to 100, VO = –10 V to +10 V, RL = 2 kΩ 30
OUTPUT
Voltage swing (V–) + 0.15 (V+) – 0.15 V
Load capacitance stability 1000 pF
ZO Closed-loop output impedance f = 10 kHz 1.3 Ω
ISC Short-circuit current Continuous to VS / 2 ±18 mA
FREQUENCY RESPONSE
BW Bandwidth, –3 dB G = 1 2.0 MHz
G = 10 640 kHz
G = 100 260
G = 1000 33
SR Slew rate G = 1, VO = ±10 V 1.2 V/µs
tS Settling time 0.01%, G = 1 to 100, VSTEP = 10 V 12 µs
0.01%, G = 1000, VSTEP = 10 V 40
0.001%, G = 1 to 100, VSTEP = 10 V 16
0.001%, G = 1000, VSTEP = 10 V 50
REFERENCE INPUT
RIN Input impedance 40 kΩ
Voltage range (V–) (V+) V
Gain to output 1 V/V
Reference gain error 0.01%
POWER SUPPLY
VS Power-supply voltage Single supply 4.5 36 V
Dual supply ±2.25 ±18
IQ Quiescent current VIN = 0 V 600 650 µA
vs temperature, TA = –40°C to +125°C 850
(1) Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).
(2) Specified by characterization.
(3) Offset drifts are uncorrelated. Input-referred offset drift is calculated using: ΔVOS(RTI) = √[ΔVOSI2 + (ΔVOSO / G)2]
(4) Input voltage range of the INA828 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and reference voltage. See Typical Characteristic curves Figure 48 through Figure 51 for more information.
(5) The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
(6) Total RTI voltage noise is equal to: eN(RTI) = √[eNI2 + (eNO / G)2]