SLLSFW9 April   2024 ISO7741TA-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics Transformer
    10. 5.10 Electrical Characteristics—5-V Supply
    11. 5.11 Supply Current Characteristics—5-V Supply
    12. 5.12 Electrical Characteristics—3.3-V Supply
    13. 5.13 Supply Current Characteristics—3.3-V Supply
    14. 5.14 Electrical Characteristics—2.5-V Supply 
    15. 5.15 Supply Current Characteristics—2.5-V Supply
    16. 5.16 Switching Characteristics—5-V Supply
    17. 5.17 Switching Characteristics—3.3-V Supply
    18. 5.18 Switching Characteristics—2.5-V Supply
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Electromagnetic Compatibility (EMC) Considerations
      2. 6.3.2 Push-Pull Converter
      3. 6.3.3 Core Magnetization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device I/O Schematics
      2. 6.4.2 Start-Up Mode
      3. 6.4.3 Operating Mode
      4. 6.4.4 Spread Spectrum Clocking
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Drive Capability
        2. 7.2.2.2 LDO Selection
        3. 7.2.2.3 Diode Selection
        4. 7.2.2.4 Capacitor Selection
        5. 7.2.2.5 Transformer Selection
          1. 7.2.2.5.1 V-t Product Calculation
          2. 7.2.2.5.2 Turns Ratio Estimate
          3. 7.2.2.5.3 Recommended Transformers
      3. 7.2.3 Application Curve
        1. 7.2.3.1 Insulation Lifetime
      4. 7.2.4 System Examples
        1. 7.2.4.1 Higher Output Voltage Designs
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DW|16
サーマルパッド・メカニカル・データ
発注情報

5.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
DW-16
CLR External clearance(1) Shortest terminal-to-terminal distance through air >8 mm
CPG External creepage(1) Shortest terminal-to-terminal distance across the package surface >8 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >17 μm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 >600 V
Material group According to IEC 60664-1 I
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 300VRMS I-IV
Rated mains voltage ≤ 600VRMS I-IV
Rated mains voltage ≤ 1000VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2121 VPK
VIOWM Maximum working isolation voltage AC voltage; Time dependent dielectric breakdown (TDDB) Test 1500 VRMS
DC voltage 2121 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM,
t = 60s (qualification);
VTEST = 1.2 x VIOTM,
t= 1s (100% production)		 7071 VPK
VIOSM Maximum surge isolation voltage(3) VIOSM ≥ 1.3 x VIMP; Tested in oil (qualification test), 1.2/50-μs waveform per IEC 62368-1  12800 VPK
qpd Apparent charge(4) Method a, After Input output safety test subgroup 2/3,
Vini = VIOTM, tini = 60s;
Vpd(m) = 1.2 x VIORM, tm = 10s		 ≤5 pC
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60s;
Vpd(m) = 1.6 x VIORM, tm = 10s		 ≤5
Method b: At routine test (100% production) and preconditioning (type test);
Vini = 1.2 x VIOTM, tini = 1s;
Vpd(m) = 1.875 x VIORM, tm = 1s (method b1) or
Vpd(m) = Vini, tm = tini (method b2)		 ≤5
CIO Barrier capacitance, input to output(5) VIO = 0.4 x sin (2πft), f = 1MHz ~1 pF
RIO Isolation resistance(5) VIO = 500V, TA = 25°C >1012 Ω
VIO = 500V, 100°C ≤ TA ≤ 125°C >1011
VIO = 500V at TS = 150°C >109
Pollution degree 2
Climatic category 55/125/21
UL 1577
VISO Maximum withstanding isolation voltage VTEST = VISO , t = 60s (qualification),
VTEST = 1.2 x VISO , t = 1s (100% production)		 5000 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed-circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.