JAJSRF7 October   2023 ISOTMP35-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Insulation Specification
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Features Description
      1. 7.3.1 Integrated Isolation Barrier and Thermal Response
      2. 7.3.2 Analog Output
      3. 7.3.3 Thermal Response
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Output Voltage Linearity
      2. 8.1.2 Load Regulation
      3. 8.1.3 Start-Up Settling Time
      4. 8.1.4 Thermal Response
      5. 8.1.5 External Buffer
      6. 8.1.6 ADC Selection and Impact on Accuracy
      7. 8.1.7 Implementation Guidelines
      8. 8.1.8 PSRR
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Insulation Lifetime
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
    2. 10.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • DFQ|7
サーマルパッド・メカニカル・データ
発注情報

8.1.7 Implementation Guidelines

Voltage clearance on the line must be respected.
A minimum of two layers is required for the ISOTMP35-Q1. Standard layer stacking can be used for a 4-layer PCB where the signal traces can run either on the top or bottom layer. Solid ground and power plane must form the inner layer. See PCB Cross-Section for a depiction of plane and trace clearance under the device.
GUID-20211110-SS0I-6TJ3-WVLD-BVTXNR7W3ZCM-low.svg Figure 8-2 PCB Cross-Section