JAJSAC1G November   2007  – November 2023 LM3481

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings: LM3481
    3. 5.3 Recommended Operating Ratings
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Overvoltage Protection
      2. 6.3.2 Bias Voltage
      3. 6.3.3 Slope Compensation Ramp
      4. 6.3.4 Frequency Adjust, Synchronization, and Shutdown
      5. 6.3.5 Undervoltage Lockout (UVLO) Pin
      6. 6.3.6 Short-Circuit Protection
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Boost Converter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Custom Design with WEBENCH Tools
          2. 7.2.1.2.2  Power Inductor Selection
          3. 7.2.1.2.3  Programming the Output Voltage and Output Current
          4. 7.2.1.2.4  Current Limit With Additional Slope Compensation
          5. 7.2.1.2.5  Power Diode Selection
          6. 7.2.1.2.6  Power MOSFET Selection
          7. 7.2.1.2.7  Input Capacitor Selection
          8. 7.2.1.2.8  Output Capacitor Selection
          9. 7.2.1.2.9  Driver Supply Capacitor Selection
          10. 7.2.1.2.10 Compensation
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Typical SEPIC Converter
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 Power MOSFET Selection
          2. 7.2.2.2.2 Power Diode Selection
          3. 7.2.2.2.3 Selection of Inductors L1 and L2
          4. 7.2.2.2.4 Sense Resistor Selection
          5. 7.2.2.2.5 SEPIC Capacitor Selection
          6. 7.2.2.2.6 Input Capacitor Selection
          7. 7.2.2.2.7 Output Capacitor Selection
        3. 7.2.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Custom Design with WEBENCH Tools
      2. 8.1.2 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Slope Compensation Ramp

The LM3481 uses a current mode control scheme. The main advantages of current mode control are inherent cycle-by-cycle current limit for the switch and simpler control loop characteristics. It is easy to parallel power stages using current mode control because current sharing is automatic. However there is a natural instability that will occur for duty cycles, D, greater than 50% if additional slope compensation is not addressed as described below.

The current mode control scheme samples the inductor current, IL, and compares the sampled signal, Vsamp, to a internally generated control signal, Vc. The current sense resistor, RSEN, as shown in the Figure 6-3, converts the sampled inductor current, IL, to the voltage signal, Vsamp, that is proportional to IL such that:

Equation 1. Vsamp = IL x RSEN

The rising and falling slopes, M1 and −M2 respectively, of Vsamp are also proportional to the inductor current rising and falling slopes, Mon and −Moff respectively. Where Mon is the inductor slope during the switch on-time and −Moff is the inductor slope during the switch off-time and are related to M1 and −M2 by:

Equation 2. M1 = Mon x RSEN
Equation 3. −M2 = −Moff x RSEN

For the boost topology:

Equation 4. Mon = VIN / L
Equation 5. −Moff = (VIN − VOUT) / L
Equation 6. M1 = [VIN / L] x RSEN
Equation 7. −M2 = [(VIN − VOUT) / L] x RSEN
Equation 8. M2 = [(VOUT − VIN) / L] x RSEN

Current mode control has an inherent instability for duty cycles greater than 50%, as shown in Figure 6-3, where the control signal slope, MC, equals zero. In Figure 6-3, a small increase in the load current causes the sampled signal to increase by ΔVsamp0. The effect of this load change, ΔVsamp1, at the end of the first switching cycle is :

Equation 9. GUID-541A9DD6-4E57-4F39-92B7-80F0B1B89A47-low.gif

From Equation 9, when D > 0.5, ΔVsamp1 will be greater than ΔVsamp0. In other words, the disturbance is divergent. So a very small perturbation in the load will cause the disturbance to increase. To ensure that the perturbed signal converges we must maintain:

Equation 10. GUID-4E0F0150-F175-4CAB-AF6F-8DECC1B30D41-low.gif
GUID-9753166A-8B99-4575-B2BD-46AF18413A1B-low.gifFigure 6-3 Subharmonic Oscillation for D>0.5
GUID-EE314C1C-4F7F-4DF4-A715-07B10611B48B-low.gifFigure 6-4 Compensation Ramp Avoids Subharmonic Oscillation

To prevent the subharmonic oscillations, a compensation ramp is added to the control signal, as shown in Figure 6-4.

With the compensation ramp, ΔVsamp1 and the convergence criteria are expressed by,

Equation 11. GUID-D09394DA-EAD8-4AA5-9F47-D03EEB64C5E0-low.gif
Equation 12. GUID-5A163D4C-E9E0-4BC0-BB27-A7EF8F2BBAD7-low.gif

The compensation ramp has been added internally in the LM3481. The slope of this compensation ramp has been selected to satisfy most applications, and its value depends on the switching frequency. This slope can be calculated using the formula:

Equation 13. MC = VSL x fS

In Equation 13, VSL is the amplitude of the internal compensation ramp and fS is the controller's switching frequency. Limits for VSL have been specified in the Electrical CharacteristicsElectrical CharacteristicsElectrical Characteristics section.

To provide the user additional flexibility, a patented scheme has been implemented inside the IC to increase the slope of the compensation ramp externally, if the need arises. Adding a single external resistor, RSL(as shown in Figure 6-6) increases the amplitude of the compensation ramp as shown in Figure 6-5.

GUID-9A1DAD61-F4A1-4728-90D6-714C2ED6DA7F-low.gifFigure 6-5 Additional Slope Compensation Added Using External Resistor RSL

Where,

Equation 14. ΔVSL = K x RSL

K = 40 µA typically and changes slightly as the switching frequency changes. Figure 6-7 shows the effect the current K has on ΔVSLand different values of RSL as the switching frequency changes.

A more general equation for the slope compensation ramp, MC, is shown below to include ΔVSL caused by the resistor RSL.

Equation 15. MC = (VSL + ΔVSL) x fS

It is good design practice to only add as much slope compensation as needed to avoid subharmonic oscillation. Additional slope compensation minimizes the influence of the sensed current in the control loop. With very large slope compensation the control loop characteristics are similar to a voltage mode regulator which compares the error voltage to a saw tooth waveform rather than the inductor current.

GUID-20230829-SS0I-MX5Q-KZGB-BNXF4W3DWWKK-low.svgFigure 6-6 Increasing the Slope of the Compensation Ramp
GUID-8C3231E4-3CAC-473C-829A-6734CD27D8D1-low.pngFigure 6-7 ΔVSL vs RSL