JAJSOR1D june   2022  – august 2023 LM5177

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Gate Driver Rise Time and Fall Time
    2. 7.2 Gate Driver Dead (Transition) Time
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power-On Reset (POR System)
      2. 8.3.2  Buck-Boost Control Scheme
        1. 8.3.2.1 Boost Mode
        2. 8.3.2.2 Buck Mode
        3. 8.3.2.3 Buck-Boost Mode
      3. 8.3.3  Power Save Mode
      4. 8.3.4  Supply Voltage Selection – VMAX Switch
      5. 8.3.5  Enable and Undervoltage Lockout
      6. 8.3.6  Oscillator Frequency Selection
      7. 8.3.7  Frequency Synchronization
      8. 8.3.8  Voltage Regulation Loop
      9. 8.3.9  Output Voltage Tracking
      10. 8.3.10 Slope Compensation
      11. 8.3.11 Configurable Soft Start
      12. 8.3.12 Peak Current Sensor
      13. 8.3.13 Current Monitoring and Current Limit Control Loop
      14. 8.3.14 Short Circuit - Hiccup Protection
      15. 8.3.15 nFLT Pin and Protections
      16. 8.3.16 Device Configuration Pin
      17. 8.3.17 Dual Random Spread Spectrum – DRSS
      18. 8.3.18 Gate Driver
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design with WEBENCH Tools
        2. 9.2.2.2  Frequency
        3. 9.2.2.3  Feedback Divider
        4. 9.2.2.4  Inductor and Current Sense Resistor Selection
        5. 9.2.2.5  Slope Compensation
        6. 9.2.2.6  Output Capacitor
        7. 9.2.2.7  Input Capacitor
        8. 9.2.2.8  UVLO Divider
        9. 9.2.2.9  Soft-Start Capacitor
        10. 9.2.2.10 MOSFETs QH1 and QL1
        11. 9.2.2.11 MOSFETs QH2 and QL2
        12. 9.2.2.12 Frequency Compensation
        13. 9.2.2.13 External Component Selection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Bi-Directional Power Backup
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Stage Layout
      2. 11.1.2 Gate Driver Layout
      3. 11.1.3 Controller Layout
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design with WEBENCH Tools
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.16 Device Configuration Pin

The resistor selection on the CFG pin is read and latched during the power-up sequence of the device. The selection cannot be changed until the voltage on the EN or UVLO reaches the falling threshold or VCC voltage drops below the VCCT-(UVLO) threshold. Table 8-1 shows the possible device configurations versus the different resistor values on the CFG pin.

Table 8-1 CFG Pin Configuration Overview
#R(CFG) / kΩDRSSSCP – Hiccup ModePSM Entry ThresholdCurrent Limit
10DISABLEDDISABLED10 %DISABLED
20.511ENABLEDDISABLED
31.3DISABLEDENABLED
41.9ENABLEDENABLED
52.7DISABLEDDISABLED10 %ENABLED
63.8ENABLEDDISABLED
75.1DISABLEDENABLED
86.5ENABLEDENABLED
98.3DISABLEDDISABLED15 %DISABLED
1010.5ENABLEDDISABLED
1113.3DISABLEDENABLED
1216.2ENABLEDENABLED
1320.5DISABLEDDISABLED15 %ENABLED
1424.9ENABLEDDISABLED
1530.1DISABLEDENABLED
1636.5ENABLEDENABLED