JAJSGF7G May   2010  – November 2018 LM98640QML-SP

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings    
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information         
    5. 6.5 Quality Conformance Inspection
    6. 6.6 LM98640QML-SP Electrical Characteristics
    7. 6.7 AC Timing Specifications
    8. 6.8 Typical Performance Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sampling Modes
        1. 7.3.1.1 Sample & Hold Mode
          1. 7.3.1.1.1 Sample & Hold Mode CLAMP/SAMPLE Adjust
        2. 7.3.1.2 CDS Mode
          1. 7.3.1.2.1 CDS Mode Bimodal Offset
          2. 7.3.1.2.2 CDS Mode CLAMP/SAMPLE Adjust
      2. 7.3.2 Input Bias and Clamping
        1. 7.3.2.1 Sample and Hold Mode Biasing
        2. 7.3.2.2 CDS Mode Biasing
        3. 7.3.2.3 VCLP DAC
      3. 7.3.3 Programmable Gain
        1. 7.3.3.1 CDS/SH Stage Gain
        2. 7.3.3.2 PGA Gain Plots
      4. 7.3.4 Programmable Analog Offset Correction
      5. 7.3.5 Analog to Digital Converter
      6. 7.3.6 LVDS Output
        1. 7.3.6.1 LVDS Output Voltage
        2. 7.3.6.2 LVDS Output Modes
        3. 7.3.6.3 TXFRM Output
          1. 7.3.6.3.1 Output Mode 1 - Dual Lane
          2. 7.3.6.3.2 Output Mode 2 - Quad Lane
      7. 7.3.7 Clock Receiver
      8. 7.3.8 Power Trimming
    4. 7.4 Device Functional Mode
      1. 7.4.1 Powerdown Modes
      2. 7.4.2 LVDS Test Modes
        1. 7.4.2.1 Test Mode 0 - Fixed Pattern
        2. 7.4.2.2 Test Mode 1 - Horizontal Gradient
        3. 7.4.2.3 Test Mode 2 - Vertical Gradient
        4. 7.4.2.4 Test Mode 3 - Lattice Pattern
        5. 7.4.2.5 Test Mode 4 - Stripe Pattern
        6. 7.4.2.6 Test Mode 5 - LVDS Test Pattern (Synchronous)
        7. 7.4.2.7 Test Mode 6 - LVDS Test Pattern (Asynchronous)
        8. 7.4.2.8 Pseudo Random Number Mode
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Writing to the Serial Registers
      3. 7.5.3 Reading the Serial Registers
      4. 7.5.4 Serial Interface Timing Details
    6. 7.6 Register Maps
      1. 7.6.1 Register Definitions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Total Ionizing Dose
      2. 8.1.2 Single Event Latch-Up and Functional Interrupt
      3. 8.1.3 Single Event Effects
    2. 8.2 Typical Application
      1. 8.2.1 Sample/Hold Mode
    3. 8.3 Initialization Set Up
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Power Planes
      2. 9.1.2 Bypass Capacitors
      3. 9.1.3 Ground Plane
      4. 9.1.4 Thermal Management
  10. 10デバイスおよびドキュメントのサポート
    1. 10.1 デバイス・サポート
      1. 10.1.1 開発サポート
        1. 10.1.1.1 評価ボード
        2. 10.1.1.2 レジスタのプログラミング用ソフトウェア
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 コミュニティ・リソース
    4. 10.4 輸出管理に関する注意事項
    5. 10.5 商標
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 Glossary
  11. 11メカニカル、パッケージ、および注文情報
    1. 11.1 エンジニアリング・サンプル

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • NBB|68
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

68-Pin QFP
Package NBB0068D
Top View
LM98640QML-SP 30064702.gif

Pin Functions

PIN NAME I/O(1) TYP RES DESCRIPTION
1 VCOM1 O A Common mode of ADC reference. Bypass with 0.1-µF capacitor to VSS33.
2 VDD33 P Analog power supply. Decouple with minimum 0.1-µF capacitor to VSS33 plane.
3 VDD33 P Analog power supply. Decouple with minimum 0.1-µF capacitor to VSS33 plane.
4 VSS33 P Analog supply return.
5 VSS33 P Analog supply return.
6 OS1- I A Analog input signal.
7 OS1+ I A Sample/Hold Mode Reference Level. Bypassed with a 0.1-µF to ground in CDS mode.
8 VSS33 P Analog supply return.
9 VCLP O A Programmable Clamp Voltage output. Normally bypassed with a 0.1-µF capacitor to VSS33.
10 VSS33 P Analog supply return.
11 OS2+ I A Sample/Hold Mode Reference Level. Bypassed with a 0.1-µF to ground in CDS mode.
12 OS2- I A Analog input signal.
13 VSS33 P Analog supply return.
14 VSS33 P Analog supply return.
15 VDD33 P Analog power supply. Decouple with minimum 0.1-µF capacitor to VSS33 plane.
16 VDD33 P Analog power supply. Decouple with minimum 0.1-µF capacitor to VSS33 plane.
17 VCOM2 O A Common mode of ADC reference. Bypass with 0.1-µF capacitor to ground.
18 VREFB2 O A Bottom of ADC reference. Bypass with a 0.1-µF capacitor to ground.
19 VREFT2 O A Top of ADC reference. Bypass with a 0.1-µF capacitor to ground.
20 VSS33 P Analog supply return.
21 VSS33 P Analog supply return.
22 VDD33 P Analog power supply. Decouple with minimum 0.1-µF capacitor to VSS33 plane.
23 VDD33 P Analog power supply. Decouple with minimum 0.1-µF capacitor to VSS33 plane.
24 VSS33 P Analog supply return.
25 SDO O D Serial Interface Data Output. (Tri-State when SEN is high)
26 SDI I D Serial Interface Data Input. (Tri-State when SEN is high)
27 SCLK I D PD Serial Interface shift register clock. (Tri-State when SEN is high)
28 SEN I D PU Active-low chip enable for the Serial Interface.
29 NC No Connection. Can be connected to VSS18.
30 CLPIN I D Input clamp signal.
31 VSS18 P Digital supply return.
32 VDD18 P Digital power supply. Decouple with minimum 0.1-µF capacitor to VSS18 plane.
33 DTM1 O D Digital Timing Monitor. If not used, can be connected to VDD18 through a 10-kΩ resistor.
34 DTM0 O D Digital Timing Monitor. If not used, can be connected to VDD18 through a 10-kΩ resistor.
35 VDD18 P Digital power supply. Decouple with minimum 0.1-µF capacitor to VSS18 plane.
36 VSS18 P Digital supply return.
37 TXFRM+ O D LVDS Frame+
38 TXFRM- O D LVDS Frame-
39 TXOUT3+ O D LVDS Data Out3+
40 TXOUT3- O D LVDS Data Out3-
41 TXOUT2+ O D LVDS Data Out2+
42 TXOUT2- O D LVDS Data Out2-
43 TXOUT1+ O D LVDS Data Out1+
44 TXOUT1- O D LVDS Data Out1-
45 TXOUT0+ O D LVDS Data Out0+
46 TXOUT0- O D LVDS Data Out0-
47 TXCLK+ O D LVDS Clock+
48 TXCLK- O D LVDS Clock-
49 VSS18 P Digital supply return.
50 VDD18 P Digital power supply. Decouple with minimum 0.1-µF capacitor to VSS18 plane.
51 ATB0 O A Analog Test Bus. If not used, can be connected to VSS18 through a 10-kΩ resistor.
52 ATB1 O A Analog Test Bus. If not used, can be connected to VSS18 through a 10-kΩ resistor.
53 VDD18 P Digital power supply. Decouple with minimum 0.1-µF capacitor to VSS18 plane.
54 VDD18 P Digital power supply. Decouple with minimum 0.1-µF capacitor to VSS18 plane.
55 VSS18 P Digital supply return.
56 VSS18 P Digital supply return.
57 INCLK- I D Clock Input. Inverting input for LVDS clocks.
58 INCLK+ I D Clock Input. Non-Inverting input for LVDS clocks.
59 VSS33 P Analog supply return.
60 VDD33 P Analog power supply. Decouple with minimum 0.1-µF capacitor to VSS33 plane.
61 VDD33 P Analog power supply. Decouple with minimum 0.1-µF capacitor to VSS33 plane.
62 VSS33 P Analog supply return.
63 IBIAS0 I A Connect with external 10-kΩ 1% resistor to IBIAS1 pin.
64 IBIAS1 I A Connect with external 10-kΩ 1% resistor to IBIAS0 pin.
65 VREFBG O A Band gap reference output. Bypass with a 0.1-µF capacitor to VSS33. Can be overdriven with external voltage source.
66 VSS33 P Analog supply return.
67 VREFT1 O A Top of ADC reference. Bypass with a 0.1-µF capacitor to VSS33.
68 VREFB1 O A Bottom of ADC reference. Bypass with a 0.1-µF capacitor to VSS33.
Exp Pad P Exposed pad must be soldered to ground plane to ensure rated performance.
(1) (I = Input), (O = Output), (IO = Bi-directional), (P = Power), (D = Digital), (A = Analog), (PU = Pull Up with an internal resistor), (PD = Pull Down with an internal resistor.).