JAJSGF7G May   2010  – November 2018 LM98640QML-SP

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings    
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information         
    5. 6.5 Quality Conformance Inspection
    6. 6.6 LM98640QML-SP Electrical Characteristics
    7. 6.7 AC Timing Specifications
    8. 6.8 Typical Performance Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sampling Modes
        1. 7.3.1.1 Sample & Hold Mode
          1. 7.3.1.1.1 Sample & Hold Mode CLAMP/SAMPLE Adjust
        2. 7.3.1.2 CDS Mode
          1. 7.3.1.2.1 CDS Mode Bimodal Offset
          2. 7.3.1.2.2 CDS Mode CLAMP/SAMPLE Adjust
      2. 7.3.2 Input Bias and Clamping
        1. 7.3.2.1 Sample and Hold Mode Biasing
        2. 7.3.2.2 CDS Mode Biasing
        3. 7.3.2.3 VCLP DAC
      3. 7.3.3 Programmable Gain
        1. 7.3.3.1 CDS/SH Stage Gain
        2. 7.3.3.2 PGA Gain Plots
      4. 7.3.4 Programmable Analog Offset Correction
      5. 7.3.5 Analog to Digital Converter
      6. 7.3.6 LVDS Output
        1. 7.3.6.1 LVDS Output Voltage
        2. 7.3.6.2 LVDS Output Modes
        3. 7.3.6.3 TXFRM Output
          1. 7.3.6.3.1 Output Mode 1 - Dual Lane
          2. 7.3.6.3.2 Output Mode 2 - Quad Lane
      7. 7.3.7 Clock Receiver
      8. 7.3.8 Power Trimming
    4. 7.4 Device Functional Mode
      1. 7.4.1 Powerdown Modes
      2. 7.4.2 LVDS Test Modes
        1. 7.4.2.1 Test Mode 0 - Fixed Pattern
        2. 7.4.2.2 Test Mode 1 - Horizontal Gradient
        3. 7.4.2.3 Test Mode 2 - Vertical Gradient
        4. 7.4.2.4 Test Mode 3 - Lattice Pattern
        5. 7.4.2.5 Test Mode 4 - Stripe Pattern
        6. 7.4.2.6 Test Mode 5 - LVDS Test Pattern (Synchronous)
        7. 7.4.2.7 Test Mode 6 - LVDS Test Pattern (Asynchronous)
        8. 7.4.2.8 Pseudo Random Number Mode
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Writing to the Serial Registers
      3. 7.5.3 Reading the Serial Registers
      4. 7.5.4 Serial Interface Timing Details
    6. 7.6 Register Maps
      1. 7.6.1 Register Definitions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Total Ionizing Dose
      2. 8.1.2 Single Event Latch-Up and Functional Interrupt
      3. 8.1.3 Single Event Effects
    2. 8.2 Typical Application
      1. 8.2.1 Sample/Hold Mode
    3. 8.3 Initialization Set Up
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Power Planes
      2. 9.1.2 Bypass Capacitors
      3. 9.1.3 Ground Plane
      4. 9.1.4 Thermal Management
  10. 10デバイスおよびドキュメントのサポート
    1. 10.1 デバイス・サポート
      1. 10.1.1 開発サポート
        1. 10.1.1.1 評価ボード
        2. 10.1.1.2 レジスタのプログラミング用ソフトウェア
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 コミュニティ・リソース
    4. 10.4 輸出管理に関する注意事項
    5. 10.5 商標
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 Glossary
  11. 11メカニカル、パッケージ、および注文情報
    1. 11.1 エンジニアリング・サンプル

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • NBB|68
サーマルパッド・メカニカル・データ
発注情報

7.6.1 Register Definitions

NOTE: Registers need to be written with baseline values after power-up to place part in a valid state.

Table 6. Register Definitions - Analog Configuration

ADDRESS
(BINARY)		 REGISTER
TITLE		 BASELINE
(BINARY)		 BIT(s) DESCRIPTION
00 0000 Main Configuration 0000 0100 [7:0] Main Configuration
[7] Not Used
[6] Coarse DAC Enable
0 Disable
1 Enable
[5] Fine DAC Enable
0 Disable
1 Enable
[4] Reserved
[3] CLPIN Gating Enable
0 CLPIN not gated by CLAMP
1 CLPIN gated by CLAMP (=logical "and" of CLPIN and CLAMP)
[2] Gain Mode Select. Selects either a 1x or 2x gain mode in the CDS/Sample/Hold Block
0 1x Gain in the CDS/Sample/Hold Block
1 2x Gain in the CDS/Sample/Hold Block
[1] Reserved. Set to 0.
[0] CDS / Sample/Hold Mode select.
0 Disabled. Correlated Double Sample Mode disabled.
1 Enabled. Correlated Double Sample Mode enabled.
00 0001 Powerdown Control 0000 0000 [7:0] Powerdown Control Register
[7] Master Powerdown
0 Fully Powered.
1 Powerdown Mode. Over rides bits [6:0].
[6] VCLP Powerdown
0 VCLP Fully Powered.
1 VCLP Powerdown Mode.
[5] Channel 2 Reference Buffer Powerdown
0 Reference Buffer Fully Powered.
1 Reference Buffer Powerdown Mode.
[4] Channel 1 Reference Buffer Powerdown
0 Reference Buffer Fully Powered.
1 Reference Buffer Powerdown Mode.
[3] Channel 2 PGA Powerdown
0 OpAmp Fully Powered.
1 OpAmp Powerdown Mode.
[2] Channel 1 PGA Powerdown
0 OpAmp Fully Powered.
1 OpAmp Powerdown Mode.
[1] Channel 2 ADC Powerdown
0 Amplifier Fully Powered.
1 Amplifier Powerdown Mode.
[0] Channel 1 ADC Powerdown
0 ADC Fully Powered.
1 ADC Powerdown Mode.
00 0010 PGA Power Trimming 0010 0100 [7:0] PGA Power Trimming Register.
[7:6] Not Used
[5:3] PGA Stage 1 Current Trimming
Tunable between 000-Weak to 111-Strong (Default 100)
[2:0] PGA Stage 2 Current Trimming
Tunable between 000-Weak to 111-Strong (Default 100)
00 0011 ADC Power Trimming 0101 1011 [7:0] ADC Power Trimming Register.
[7:6] Reserved. Set to 2'b01.
[5:3] ADC Current Trimming 2(Not Binary Weighted)
000 25% Power
001 50% Power
011 75% Power (Default)
111 100% Power
[2:0] ADC Current Trimming 1 (Not Binary Weighted)
000 25% Power
001 50% Power
011 75% Power (Default)
111 100% Power
00 0100 VCLP Control 0111 0100 [7:0] Voltage Clamp Buffer Control Register.
[7] Not Used
[6] Buffer Enable
0 Disabled. Resistor Ladder is driving VCLP pin.
1 Enabled. Resistor Ladder is buffered to VCLP pin.
[5] VCLP Enable
0 Disabled. VCLP pin can be externally driven.
1 Enabled. VCLP pin is in output mode.
[4:0] Voltage Level of VCLP pin.
VCLP range is 200mV to 3.1V in 100mV steps for (binary) settings 00000 to 11101. Settings 11110 and 11111 are not used.
00 0101 LVDS Output Modes 0000 1110 [7:0] LVDS Output Configuration Register.
[7] Serializer Data Reset. (Not self-clearing)
[6:4] Not Used.
[3] LVDS Output Mode
0 Dual Lane Mode (see Output Mode 1 - Dual Lane)
1 Quad Lane Mode (see Output Mode 2 - Quad Lane)
[2] LVDS Driver Enable.
0 LVDS Drivers Disabled
1 LVDS Drivers Enabled
(Note: In Dual Lane Mode TX0 and TX3 are disabled regardless of driver enable)
[1:0] LVDS Amplitude and Common Mode Voltage.
00 250mV (1.2V DC Offset)
01 300mV (1.2V DC Offset)
10 350mV (1.1V DC Offset)
11 400mV (1.1V DC Offset)
00 0110 Sample & Hold 1000 0001 [7:0] Sample & Hold Mode Register
[7] Sample & Hold Mode Enable
0 Disabled.
1 Enabled.
[6:3] Not Used.
[2:1] Reference Buffer Power Level
11 100% Power. Used for FINCLK = 20-40MHz.
10 60% Power. Used for FINCLK = 10-20MHz.
01 60% Power. Used for FINCLK = 10-20MHz.
00 30% Power. Used for FINCLK = 5-10MHz.
[0] Reserved.
00 0111 Status 0000 0000 [7:0] Status Register. (Read Only)
[7:1] Not Used.
[0] False Lock Detect.
Indicates if DLL is locked into a half frequency state.
00 1001 Clock Monitor 0000 0000 [7:0] Internal Clock Signal Monitor Register
[7:5] Not Used.
[4:3] Enable and select clocks to be monitored on the Digital Timing Monitor. (DTM)
00 Disable Digital Timing Monitor Pins (DTM0, DTM1)
01 Send CLAMPEVEN to DTM0 pin, and SAMPLEEVEN to DTM1
10 Send CLAMPODD to DTM0 pin, and SAMPLEODD to DTM1
11 Send ODD tag and ADC Clock to the DTM.
[2:0] Reserved. Set to 000.

Table 7. Register Definitions - GAIN & Offset DAC Configuration

ADDRESS
(BINARY)		 REGISTER
TITLE		 BASELINE
(BINARY)		 BIT(s) DESCRIPTION
01 0000 CDAC1 0000 0000 [7:0] Channel 1 Coarse DAC Register.
[7:1] Not Used.
[0] Bit 8 of Channel 1 Coarse DAC Offset Value.
01 0001 CDAC1 1111 1111 [7:0] Channel 1 Coarse DAC Offset Value bits 7:0.
01 0010 FDAC1 0000 0000 [7:0] Channel 1 Fine DAC Register.
[7:1] Not Used.
[0] Bit 8 of Channel 1 Fine DAC Offset Value.
01 0011 FDAC1 1111 1111 [7:0] Channel 1 Fine DAC Offset Value bits 7:0.
01 0101 PGA1 0110 0001 [7:0] Channel 1 Programmable Gain Amplifier Value.
01 1000 CDAC2 0000 0000 [7:0] Channel 2 Coarse DAC Register.
[7:1] Not Used.
[0] Bit 8 of Channel 2 Coarse DAC Offset Value.
01 1001 CDAC2 1111 1111 [7:0] Channel 2 Coarse DAC Offset Value bits 7:0.
01 1010 FDAC2 0000 0000 [7:0] Channel 2 Fine DAC Register.
[7:1] Not Used.
[0] Bit 8 of Channel 2 Fine DAC Offset Value.
01 1011 FDAC2 1111 1111 [7:0] Channel 2 Fine DAC Offset Value bits 7:0.
01 1100 PGA2 0110 0001 [7:0] Channel 2 Programmable Gain Amplifier Value.

Table 8. Register Definitions - Timing Configuration

ADDRESS
(BINARY)		 REGISTER
TITLE		 BASELINE
(BINARY)		 BIT(s) DESCRIPTION
10 0000 Clamp Start 0000 1000 [7:0] Clamp Start Register.
[7:6] Not Used.
[5:0] CLAMP Starting Index. 0-63d position for rising edge of CLAMP signal. Valid only in CDS Mode.
10 0001 Clamp End 0001 1100 [7:0] Clamp End Register.
[7:6] Not Used.
[5:0] CLAMP End Index. 0-63d position for falling edge of CLAMP signal. Valid only in CDS Mode.
10 0010 Sample Start 0010 1000 [7:0] Sample Start Register.
[7:6] Not Used.
[5:0] SAMPLE starting Index. 0-63d position for rising edge of SAMPLE signal.
10 0011 Sample End 0011 1100 [7:0] Sample End Register.
[7:6] Not Used.
[5:0] SAMPLE End Index. 0-63d position for falling edge of SAMPLE signal.
10 0101 INCLK Range 0000 0010 [7:0] INCLK Range Register.
[7] Not Used.
[6:4] INCLK Range.
000 25 to 40 MHz Operation
001 14 to 25 MHz Operation
010 10 to 14 MHz Operation
011 7.5 to 10 MHz Operation
100 6 to 7.5 MHz Operation
101 5 to 6 MHz Operation
110 Not Used
111 Not Used
[3:2] Not Used.
[1:0] DLL Range
11 Reserved
10 14 to 40 MHz Operation
01 7.5 to 14 MHz Operation
00 5 to 7.5 MHz Operation
10 1000 DLL Configuration 0000 1111 [7:0] DLL Configuration Register
[7:1] Reserved
[0] DLL Reset. (Self Clearing)

Table 9. Register Definitions - Digital Configuration

ADDRESS
(BINARY)		 REGISTER
TITLE		 BASELINE
(BINARY)		 BIT(s) DESCRIPTION
11 0000 Test Pattern Start 0000 0000 [15:8] Upper 8 bits of the Test Pattern start value. Specifies the number of pixels after the leading edge of CLPIN to the Valid Pixel region.
11 0001 Test Pattern Start 0000 0000 [7:0] Lower 8 bits of the Test Pattern start value. Specifies the number of pixels after the leading edge of CLPIN to the Valid Pixel region.
11 0010 Test Pattern Width 0000 0000 [15:8] Upper 8 bits of the Test Pattern Width value. Specifies, in number of pixels, the width of the Valid Pixel region.
11 0011 Test Pattern Width 0000 0000 [7:0] Lower 8 bits of the Test Pattern Width value. Specifies, in number of pixels, the width of the Valid Pixel region.
11 0100 Test Pattern Control 0000 0000 [7:0] Test Pattern Control Register.
[7] Programmable Pattern Switch
0 Disabled. Normal LVDS output operation.
1 Enabled. AFE outputs LVDS test patterns.
[6:4] Test Pattern Mode
000 Fixed Code
001 Horizontal Gradient Scan (Main Scan)
010 Vertical Gradient Scan (Sub Scan)
011 Grid Scan (Lattice Pattern)
100 Strip Pattern
101 LVDS Test Pattern. (Synchronous to CLPIN)
110 LVDS Test Pattern. (Asynchronous)
111 Not Used.
[3] Pseudo Random Pattern Enable.
Overrides Programmable Patter Switch setting (bit 7). Normally only one should be on.
[2] Load Seed Enable.
When set, the seed value in the Test Pattern Value Register is loaded in the LFSR at the leading edge of CLPIN.
[1:0] Test Pattern Output Channel Select.
00 Both Channels
01 Channel 1
10 Channel 2
11 Not Used
11 0101 Test Pattern Pitch 0000 0000 [7:0] Test Pattern pitch, specifies number of pixels for H Gradient pattern and Stripe pattern, or number of lines in the V Gradient pattern, or specifies pixels & lines in the Lattice pattern.
11 0110 Test Pattern Step 0000 0000 [7:0] Test Pattern Step Code. Specifies step size in LSB codes the pattern is incremented in H Gradient and V Gradient pattern. In Lattice and Stripe pattern it specifies the code during the lower step.
11 0111 Test Pattern Channel Offset 0000 0000 [7:0] Test Pattern Channel Offset Register.
[7:4] Not Used.
[3:0] Test Pattern Channel Offset. This specifies the number of lines the pattern on Channel 2 is delayed from Channel 1. This offset is maintained throughout the pattern.
11 1000 Test Pattern Value 0000 0000 [15:8] Upper 8 bits of Test Pattern Value Register. Specifies the upper 8 bits of the test value code during Fixed Pattern and LVDS test, initial value during H Gradient & V Gradient pattern, and higher value in the Lattice and Stripe Pattern.
11 1001 Test Pattern Value 0000 0000 [7:0] Lower 6 bits of Test Pattern Value Register. Specifies the lower 6 bits of the test code value during Fixed Pattern and LVDS test, initial value during H Gradient & V Gradient pattern, and higher value in the Lattice and Stripe Pattern.
11 1100 Digital Configuration 0000 0000 [7:0] Serial Communication Configuration Register.
[7:1] Not Used.
[0] Micro-Wire Automatic Read Disable.
0 Read data is always sent out on SDO during the first 8 SCLK cycles.
The register is selected by the register address in the previous cycle. (read or write)
1 Automatic read is disabled.
To read from a register two cycles need to be initiated by the master, first cycle should be a read with the correct register address and second can be a dummy read or read from another address or a write cycle, and the data is sent first 8 SCLK of the second cycle. After a write command SDO remains in Tri-State during first 8 SCLK.
11 1101 Test & Scan Control 0000 0000 [7:0] Test & Scan Control Register
[7:6] Not Used.
[5] Test Pattern Voting Switch.
0 Enable. Circuit Redundancy Voting is active.
1 Disable. First redundancy block output is used.
[4] Micro-wire Voting Switch.
0 Enable. Circuit Redundancy Voting is active.
1 Disable. First Micro-wire block output is used.
[3] Not Used.
[2] Test Reset. Resets the test block when High, normal test block function when Low. This bit is not self-clearing.
[1] Test Mode Enable.
0 Disable.
1 Enable. Needed to run Test Pattern functions.
[0] Not Used.
11 1110 Device ID 0100 1000 [7:0] Device Revision ID. Engineering samples might be x01 or x47.