JAJSO15A february   2022  – june 2023 LMK1D1208I

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fail-Safe Input
      2. 9.3.2 Input Stage Configurability
      3. 9.3.3 Dual Output Bank
      4. 9.3.4 I2C
        1. 9.3.4.1 I2C Address Assignment
      5. 9.3.5 LVDS Output Termination
      6. 9.3.6 Input Termination
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Enable Control
      2. 9.4.2 Bank Input Selection
      3. 9.4.3 Bank Mute Control
      4. 9.4.4 Output Enable Control
      5. 9.4.5 Output Amplitude Selection
    5. 9.5 Programming
    6. 9.6 Register Maps
      1. 9.6.1 LMK1D1208I Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.6 Input Termination

The LMK1D1208I inputs can be interfaced with LVDS, LVPECL, HCSL or LVCMOS drivers.

Figure 9-3 and Figure 9-4 show how LVDS drivers can be connected to LMK1D1208I inputs with DC coupling and AC coupling, respectively.

GUID-F00A73CF-4FF7-42C4-ACBE-0A4D08BB8A36-low.gifFigure 9-3 LVDS Clock Driver Connected to LMK1D1208I Input (DC-Coupled)
GUID-20BFB2EF-870D-4823-8AAE-26878048414C-low.gifFigure 9-4 LVDS Clock Driver Connected to LMK1D1208I Input (AC-Coupled)

Figure 9-5 shows how to connect LVPECL inputs to the LMK1D1208I. The series resistors are required to reduce the LVPECL signal swing if the signal swing is >1.6 VPP.

GUID-E024385E-15B1-433F-8ACB-C57964B4B3FD-low.gifFigure 9-5 LVPECL Clock Driver Connected to LMK1D1208I Input

Figure 9-6 shows how to couple a LVCMOS clock input to the LMK1D1208I directly.

GUID-739304A8-DBAE-4FBC-8DDD-C640914F128A-low.gifFigure 9-6 1.8-V, 2.5-V, or 3.3-V LVCMOS Clock Driver Connected to LMK1D1208I Input

For unused input, TI recommends grounding both input pins (INP, INN) using 1-kΩ resistors.