9.2.2.1 PLL Loop Filter Design
The EVM software tool TICS Pro/Oscillator Programming Tool can be used to aid loop filter design. The Easy Configuration GUI is able to generate a suggested set of loop filter values given a desired output frequency. The tool recommends a PLL configuration that is designed to minimize jitter. As of the publication of this document, it is not yet able to optimize for desired tuning range in DCXO mode. When configuring the device for operation in DCXO mode, TI recommends using the software suggested loop filter settings as a starting point and then perform the procedure described in Detailed Design Procedure to optimize the PLL configuration to suit the application needs.
A general set of loop filter design guidelines are given below:
- There are many device configurations to achieve the desired output frequency from a device. However there are some optimizations and trade-offs to be considered.
- The guidelines below may be followed when configuring PLL related dividers or other related registers:
- For lowest possible in-band PLL flat noise, maximize phase detector frequency to minimize N divide value.
- For fractional divider values, keep the denominator at highest value possible to minimize spurs. It is also best to use a higher order modulator whenever possible for the same reason.
- As a rule of thumb, keep the phase detector frequency approximately between 10 × PLL loop bandwidth and 100 × PLL loop bandwidth. A phase detector frequency less than 5 × PLL bandwidth may be unstable.
- While designing the loop filter, adjusting the charge pump current or N value can help with loop filter component selection. Lower charge pump currents and larger N values result in smaller component values but may increase impacts of leakage and reduce PLL phase noise performance.
- A more detailed understanding of loop filter design can be found in Dean Banerjee's PLL Performance, Simulation, and Design.