JAJSDF7A January 2017 – May 2017 LMK61E0M
PRODUCTION DATA.
The PLL_FRACDEN_BY0 register is described in the following table.
BIT NO. | FIELD | TYPE | RESET | EEPROM | DESCRIPTION |
---|---|---|---|---|---|
[7:0] | PLL_DEN[7:0] | RW | 0x00 | Y | PLL Fractional Divider Denominator Byte 0. Bits [7:0]. |