JAJSPW5B November   2023  – February 2024 LMKDB1108 , LMKDB1120

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SMBus Timing Requirements
    7. 6.7 SBI Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Features
        1. 8.3.1.1 Running Input Clocks When Device is Powered Off
        2. 8.3.1.2 Fail-Safe Inputs
        3. 8.3.1.3 Internal Termination for Clock Inputs
        4. 8.3.1.4 AC-Coupled or DC-Coupled Clock Inputs
      2. 8.3.2 Flexible Power Sequence
        1. 8.3.2.1 PWRDN# Assertion and Deassertion
        2. 8.3.2.2 OE# Assertion and Deassertion
        3. 8.3.2.3 PWRGD Assertion
        4. 8.3.2.4 Clock Input and PWRGD/PWRDN# Behaviors When Device Power is Off
      3. 8.3.3 LOS and OE
        1. 8.3.3.1 Additional OE# Pins for LMKDB1120 and Backward Compatibility
        2. 8.3.3.2 Synchronous OE
        3. 8.3.3.3 OE Control
        4. 8.3.3.4 Automatic Output Disable
        5. 8.3.3.5 LOS Detection
      4. 8.3.4 Output Features
        1. 8.3.4.1 Double Termination
        2. 8.3.4.2 Programmable Output Slew Rate
        3. 8.3.4.3 Programmable Output Swing
        4. 8.3.4.4 Accurate Output Impedance
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Mode
      2. 8.4.2 SBI Mode
      3. 8.4.3 Pin Mode
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10LMKDB1120 Registers
  12. 11LMKDB1108 Registers
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 LMKDB1108 Registers

Table 11-1 lists the memory-mapped registers for the LMKDB1108 registers. All register offset addresses not listed in Table 11-1 must be considered as reserved locations and the register contents must not be modified.

Table 11-1 LMKDB1108 Registers
OffsetAcronymRegister NameSection
0hR0Output Enable Control for CLK2 through CLK7Section 11.1
1hR1Output Enable Control for CLK0 and CLK1Section 11.2
2hR2OE Pin Readback for CLK2 through CLK7Section 11.3
3hR3OE Pin Readback for CLK0 and CLK1Section 11.4
4hR4AOD Enable Control and SBI_EN ReadbackSection 11.5
5hR5Device InfoSection 11.6
6hR6Device Info (cont.)Section 11.7
7hR7SMBus Byte CounterSection 11.8
8hR8SBI Mask for CLK2 through CLK7Section 11.9
9hR9SBI Mask for CLK0 and CLK1Section 11.10
BhR11SBI Mask Readback for CLK0 through CLK5Section 11.11
ChR12SBI Mask Readback for CLK6 and CLK7Section 11.12
11hR17Output AmplitudeSection 11.13
12hR18Input Configuration, Save Config in PD, SMB SDATA Monitoring, and LOS ReadbackSection 11.14
14hR20Output Slew Rate Select MSB for CLK2 through CLK7Section 11.15
15hR21Output Slew Rate Select MSB for CLK0 and CLK1Section 11.16
26hR38Non-clearable SMBUS Write LockSection 11.17
27hR39LOS Event Status and Clearable SMBus Write LockSection 11.18
35hR53Slew Rate Mode Control SelectionSection 11.19
62hR98Output Slew Rate Select LSB for CLK0 through CLK7Section 11.20

Complex bit access types are encoded to fit into small table cells. Table 11-2 shows the codes that are used for access types in this section.

Table 11-2 LMKDB1108 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
RCR
C		Read
to Clear
Write Type
WWWrite
W1CW
1C		Write
1 to clear
WSCWWrite
Reset or Default Value
-nValue after reset or the default value

11.1 R0 Register (Offset = 0h) [Reset = EEh]

R0 is shown in Table 11-3.

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Table 11-3 R0 Register Field Descriptions
BitFieldTypeResetDescription
7CLK_EN_2R/W1h Output Enable for CLK2
0h = Output Disabled (low/low)
1h = Output Enabled
6CLK_EN_3R/W1h Output Enable for CLK3
0h = Output Disabled (low/low)
1h = Output Enabled
5CLK_EN_4R/W1h Output Enable for CLK4
0h = Output Disabled (low/low)
1h = Output Enabled
4RESERVEDR0h Reserved
3CLK_EN_5R/W1h Output Enable for CLK5
0h = Output Disabled (low/low)
1h = Output Enabled
2CLK_EN_6R/W1h Output Enable for CLK6
0h = Output Disabled (low/low)
1h = Output Enabled
1CLK_EN_7R/W1h Output Enable for CLK7
0h = Output Disabled (low/low)
1h = Output Enabled
0RESERVEDR0h Reserved

11.2 R1 Register (Offset = 1h) [Reset = 24h]

R1 is shown in Table 11-4.

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Table 11-4 R1 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5CLK_EN_0R/W1h Output Enable for CLK0
0h = Output Disabled (low/low)
1h = Output Enabled
4:3RESERVEDR0h Reserved
2CLK_EN_1R/W1h Output Enable for CLK1
0h = Output Disabled (low/low)
1h = Output Enabled
1:0RESERVEDR0h Reserved

11.3 R2 Register (Offset = 2h) [Reset = 00h]

R2 is shown in Table 11-5.

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Table 11-5 R2 Register Field Descriptions
BitFieldTypeResetDescription
7RB_OEb_2R0h Status of OEb2
6RB_OEb_3R0h Status of OEb3
5RB_OEb_4R0h Status of OEb4
4RESERVEDR0h Reserved
3RB_OEb_5R0h Status of OEb5
2RB_OEb_6R0h Status of OEb6
1RB_OEb_7R0h Status of OEb7
0RESERVEDR0h Reserved

11.4 R3 Register (Offset = 3h) [Reset = 00h]

R3 is shown in Table 11-6.

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Table 11-6 R3 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5RB_OEb_0R0h Status of OEb0
4:3RESERVEDR0h Reserved
2RB_OEb_1R0h Status of OEb1
1:0RESERVEDR0h Reserved

11.5 R4 Register (Offset = 4h) [Reset = 10h]

R4 is shown in Table 11-7.

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Table 11-7 R4 Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0h Reserved
4AOD_ENABLER/W1h Enable automatic output disable (AOD) to low/low when LOS event is detected. Refer to section "Automatic Output Disable" for more information.
0h = Disabled (DC Coupled)
1h = Enabled (AC Coupled)
3:1RESERVEDR0h Reserved
0RB_SBI_ENQR0h Status of SBI_ENQ

11.6 R5 Register (Offset = 5h) [Reset = 0Ah]

R5 is shown in Table 11-8.

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Table 11-8 R5 Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0h Reserved
3:0VENDOR_IDRAh Vendor ID

11.7 R6 Register (Offset = 6h) [Reset = 08h]

R6 is shown in Table 11-9.

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Table 11-9 R6 Register Field Descriptions
BitFieldTypeResetDescription
7:0DEV_IDR8h Device ID

11.8 R7 Register (Offset = 7h) [Reset = 07h]

R7 is shown in Table 11-10.

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Table 11-10 R7 Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0h Reserved
4:0SMBUS_BCR/W7h SMBUS Block Read Byte Count

11.9 R8 Register (Offset = 8h) [Reset = 00h]

R8 is shown in Table 11-11.

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Table 11-11 R8 Register Field Descriptions
BitFieldTypeResetDescription
7SBI_MASK_2R/W0h Mask off Side-Band Disable for CLK2
6SBI_MASK_3R/W0h Mask off Side-Band Disable for CLK3
5SBI_MASK_4R/W0h Mask off Side-Band Disable for CLK4
4RESERVEDR0h Reserved
3SBI_MASK_5R/W0h Mask off Side-Band Disable for CLK5
2SBI_MASK_6R/W0h Mask off Side-Band Disable for CLK6
1SBI_MASK_7R/W0h Mask off Side-Band Disable for CLK7
0RESERVEDR0h Reserved

11.10 R9 Register (Offset = 9h) [Reset = 00h]

R9 is shown in Table 11-12.

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Table 11-12 R9 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5SBI_MASK_0R/W0h Mask off Side-Band Disable for CLK0
4:3RESERVEDR0h Reserved
2SBI_MASK_1R/W0h Mask off Side-Band Disable for CLK1
1:0RESERVEDR0h Reserved

11.11 R11 Register (Offset = Bh) [Reset = EEh]

R11 is shown in Table 11-13.

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Table 11-13 R11 Register Field Descriptions
BitFieldTypeResetDescription
7SBI_CLK_2R1h Readback of Side-Band Disable for CLK5
6SBI_CLK_3R1h Readback of Side-Band Disable for CLK4
5SBI_CLK_4R1h Readback of Side-Band Disable for CLK3
4RESERVEDR0h Reserved
3SBI_CLK_5R1h Readback of Side-Band Disable for CLK2
2SBI_CLK_6R1h Readback of Side-Band Disable for CLK1
1SBI_CLK_7R1h Readback of Side-Band Disable for CLK0
0RESERVEDR0h Reserved

11.12 R12 Register (Offset = Ch) [Reset = 24h]

R12 is shown in Table 11-14.

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Table 11-14 R12 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5SBI_CLK_0R1h Readback of Side-Band Disable for CLK7
4:3RESERVEDR0h Reserved
2SBI_CLK_1R1h Readback of Side-Band Disable for CLK6
1:0RESERVEDR0h Reserved

11.13 R17 Register (Offset = 11h) [Reset = 66h]

R17 is shown in Table 11-15.

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Table 11-15 R17 Register Field Descriptions
BitFieldTypeResetDescription
7:4AMP_1R/W6h Global Differential output Control 0.6V~1V 25mV/step Default = 0.8V
0h = 600 mV
1h = 625 mV
2h = 650 mV
3h = 675 mV
4h = 700 mV
5h = 725 mV
6h = 750 mV
7h = 775 mV
8h = 800 mV
9h = 825 mV
Ah = 850 mV
Bh = 875 mV
Ch = 900 mV
Dh = 925 mV
Eh = 950 mV
Fh = 975 mV
3:0RESERVEDR0h Reserved

11.14 R18 Register (Offset = 12h) [Reset = 08h]

R18 is shown in Table 11-16.

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Table 11-16 R18 Register Field Descriptions
BitFieldTypeResetDescription
7RX_EN_AC_INPUTR/W0h Enable receiver bias when CLKIN is AC coupled
0h = DC Coupled Input
1h = AC Coupled Input
6RX_EN_RTERM_LSBR/W0h Enable/Disables termination resistors on CLKIN1
0h = Disabled
1h = Enabled
5RESERVEDR0h Reserved
4RESERVEDR0h Reserved
3PD_RESTOREBR/W1h Save Configuration in Power Down
0h = Config Cleared
1h = Config Saved
2:1RESERVEDR0h Reserved
0LOSb_RBR0h Real time read back of loss detect block output
0h = LOS Event Detected
1h = LOS Event Not-Detected

11.15 R20 Register (Offset = 14h) [Reset = EEh]

R20 is shown in Table 11-17.

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Table 11-17 R20 Register Field Descriptions
BitFieldTypeResetDescription
7SLEWRATE_SEL_CLK2_MSBR/W1h MSB CLK2 slew rate select
6SLEWRATE_SEL_CLK3_MSBR/W1h MSB CLK3 slew rate select
5SLEWRATE_SEL_CLK4_MSBR/W1h MSB CLK4 slew rate select
4RESERVEDR0h Reserved
3SLEWRATE_SEL_CLK5_MSBR/W1h MSB CLK5 slew rate select
2SLEWRATE_SEL_CLK6_MSBR/W1h MSB CLK6 slew rate select
1SLEWRATE_SEL_CLK7_MSBR/W1h MSB CLK7 slew rate select
0RESERVEDR0h Reserved

11.16 R21 Register (Offset = 15h) [Reset = 24h]

R21 is shown in Table 11-18.

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Table 11-18 R21 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5SLEWRATE_SEL_CLK0_MSBR/W1h MSB CLK0 slew rate select
4:3RESERVEDR0h Reserved
2SLEWRATE_SEL_CLK1_MSBR/W1h MSB CLK1 slew rate select
1:0RESERVEDR0h Reserved

11.17 R38 Register (Offset = 26h) [Reset = 00h]

R38 is shown in Table 11-19.

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Table 11-19 R38 Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0h Reserved
0WRITE_LOCKR0h Non-clearable SMBus Write Lock bit. When written to one, the SMBus control registers cannot be written to. This bit can only be cleared by recycling power.
0h = SMBus Not Locked for Writing
1h = SMBus Locked for Writing

11.18 R39 Register (Offset = 27h) [Reset = 00h]

R39 is shown in Table 11-20.

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Table 11-20 R39 Register Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR0h Reserved
1LOS_EVTR/W0h LOS Event Status. When high, indicates that a LOS event is detected. Can be cleared by writing a 1 to the bit.
0h = Not LOS Event Detected
1h = LOS Event Detected
0WRITE_LOCK_RW1CR0h Clearable SMBus Write Lock bit. When written to one, the SMBus control registers cannot be written to. This bit can be cleared by writing a 1 to the bit.
0h = SMBus Not Locked for Writing
1h = SMBus Locked for Writing

11.19 R53 Register (Offset = 35h) [Reset = 00h]

R53 is shown in Table 11-21.

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Table 11-21 R53 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5SLEWRATE_CTRL_MODER/WSC0h Sets which mode is used to change the outputs slew rates
0h = Pin mode
1h = SMBus mode
4:0RESERVEDR0h Reserved

11.20 R98 Register (Offset = 62h) [Reset = 00h]

R98 is shown in Table 11-22.

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Table 11-22 R98 Register Field Descriptions
BitFieldTypeResetDescription
7SLEWRATE_SEL_CLK7_LSBR/W0h LSB CLK7 Slew Rate Control
6SLEWRATE_SEL_CLK6_LSBR/W0h LSB CLK6 Slew Rate Control
5SLEWRATE_SEL_CLK5_LSBR/W0h LSB CLK5 Slew Rate Control
4SLEWRATE_SEL_CLK4_LSBR/W0h LSB CLK4 Slew Rate Control
3SLEWRATE_SEL_CLK3_LSBR/W0h LSB CLK3 Slew Rate Control
2SLEWRATE_SEL_CLK2_LSBR/W0h LSB CLK2 Slew Rate Control
1SLEWRATE_SEL_CLK1_LSBR/W0h LSB CLK1 Slew Rate Control
0SLEWRATE_SEL_CLK0_LSBR/W0h LSB CLK0 Slew Rate Control