JAJSPW5B November   2023  – February 2024 LMKDB1108 , LMKDB1120

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SMBus Timing Requirements
    7. 6.7 SBI Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Features
        1. 8.3.1.1 Running Input Clocks When Device is Powered Off
        2. 8.3.1.2 Fail-Safe Inputs
        3. 8.3.1.3 Internal Termination for Clock Inputs
        4. 8.3.1.4 AC-Coupled or DC-Coupled Clock Inputs
      2. 8.3.2 Flexible Power Sequence
        1. 8.3.2.1 PWRDN# Assertion and Deassertion
        2. 8.3.2.2 OE# Assertion and Deassertion
        3. 8.3.2.3 PWRGD Assertion
        4. 8.3.2.4 Clock Input and PWRGD/PWRDN# Behaviors When Device Power is Off
      3. 8.3.3 LOS and OE
        1. 8.3.3.1 Additional OE# Pins for LMKDB1120 and Backward Compatibility
        2. 8.3.3.2 Synchronous OE
        3. 8.3.3.3 OE Control
        4. 8.3.3.4 Automatic Output Disable
        5. 8.3.3.5 LOS Detection
      4. 8.3.4 Output Features
        1. 8.3.4.1 Double Termination
        2. 8.3.4.2 Programmable Output Slew Rate
        3. 8.3.4.3 Programmable Output Swing
        4. 8.3.4.4 Accurate Output Impedance
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Mode
      2. 8.4.2 SBI Mode
      3. 8.4.3 Pin Mode
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10LMKDB1120 Registers
  12. 11LMKDB1108 Registers
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 SMBus Timing Requirements

100-kHz CLASS 400-kHz CLASS UNIT
MIN MAX MIN MAX
fSMB SMBus Operating Frequency 10 100 10 400 kHz
fBUF Bus free time between STOP and START condition 4.7 – 1.3 – μs
tHD_STA Hold time after (REPEATED) START condition 4.0 – 0.6 – μs
tSU_STA REPEATED START condition setup time 4.7 – 0.6 – μs
tSU_STO STOP condition setup time 4.0 – 0.6 – μs
tHD_DAT Data hold time 0 – 0 – ns
tSU_DAT Data setup time 250 – 100 – ns
tTIMEOUT Detect clock low timeout 25 35 25 35 ms
tLOW Clock low period 4.7 – 1.3 – μs
tHIGH Clock high period 4.0 50 0.6 50 μs
tLOW_SEXT Cumulative clock low extend time (secondary device) – 25 – 25 ms
tLOW_PEXT Cumulative clock low extend time (primary device) – 10 – 10 ms
tF Clock/Data Fall Time – 300 – 300 ns
tR Clock/Data Rise Time – 1000 – 300 ns
tSPIKE Noise spike suppression time – – 0 50 ns
tPOR Time in which a device must be operational after power-on reset 500 500 ms