JAJSPW5B November   2023  – February 2024 LMKDB1108 , LMKDB1120

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SMBus Timing Requirements
    7. 6.7 SBI Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Features
        1. 8.3.1.1 Running Input Clocks When Device is Powered Off
        2. 8.3.1.2 Fail-Safe Inputs
        3. 8.3.1.3 Internal Termination for Clock Inputs
        4. 8.3.1.4 AC-Coupled or DC-Coupled Clock Inputs
      2. 8.3.2 Flexible Power Sequence
        1. 8.3.2.1 PWRDN# Assertion and Deassertion
        2. 8.3.2.2 OE# Assertion and Deassertion
        3. 8.3.2.3 PWRGD Assertion
        4. 8.3.2.4 Clock Input and PWRGD/PWRDN# Behaviors When Device Power is Off
      3. 8.3.3 LOS and OE
        1. 8.3.3.1 Additional OE# Pins for LMKDB1120 and Backward Compatibility
        2. 8.3.3.2 Synchronous OE
        3. 8.3.3.3 OE Control
        4. 8.3.3.4 Automatic Output Disable
        5. 8.3.3.5 LOS Detection
      4. 8.3.4 Output Features
        1. 8.3.4.1 Double Termination
        2. 8.3.4.2 Programmable Output Slew Rate
        3. 8.3.4.3 Programmable Output Swing
        4. 8.3.4.4 Accurate Output Impedance
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Mode
      2. 8.4.2 SBI Mode
      3. 8.4.3 Pin Mode
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10LMKDB1120 Registers
  12. 11LMKDB1108 Registers
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.2 SBI Mode

Side-Band Interface (SBI) is a simple 3-wire or 4-wire serial interface which consists of SHFT_LD#, SBI_IN, SBI_CLK and SBI_OUT (optional) pins. When the SHFT_LD# pin is high, the rising edge of SBI_CLK clocks SBI_IN into a shift register. After shifting data, the falling edge of SHFT_LD# loads the shift register contents into the output register. SBI registers can be shifted out through SBI_OUT pin to form daisy chain topology.

Enabling SBI mode does not disable SMBus. SBI registers can be accessed while PWRGD/PWRDN# pin is low.

GUID-20231203-SS0I-7B15-BKDD-CLHR10LVG4MP-low.svg Figure 8-8 SBI Control Logic
GUID-20231203-SS0I-MJGZ-SS5H-QDTMC8VWWNF0-low.svg Figure 8-9 SBI Star Topology
GUID-20231203-SS0I-034C-BR3V-JQDGD6VRCNH2-low.svg Figure 8-10 SBI Daisy Chain Topology

SBI register sequence:

  • LMKDB1120: SBI_IN – CLK0, CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, CLK8, CLK9, CLK10, CLK11, CLK12, CLK13, CLK14, CLK15, CLK16, CLK17, CLK18, CLK19 – SBI_OUT
  • LMKDB1108: SBI_IN – CLK7, CLK6, CLK5, CLK4, CLK3, CLK2, CLK1, CLK0 – SBI_OUT
  • LMKDB1104: SBI_IN – CLK3, CLK2, CLK1, CLK0