JAJSIE3B December   2019  – December 2022 LMR36506

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD (Commercial) Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 System Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable, Start-up, and Shutdown
      2. 8.3.2  Adjustable Switching Frequency (with RT)
      3. 8.3.3  Power-Good Output Operation
      4. 8.3.4  Internal LDO, VCC UVLO, and VOUT/BIAS Input
      5. 8.3.5  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Terminal)
      6. 8.3.6  Output Voltage Selection
      7. 8.3.7  Soft Start and Recovery from Dropout
        1. 8.3.7.1 Recovery from Dropout
      8. 8.3.8  Current Limit and Short Circuit
      9. 8.3.9  Thermal Shutdown
      10. 8.3.10 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 CCM Mode
        2. 8.4.3.2 Auto Mode - Light Load Operation
          1. 8.4.3.2.1 Diode Emulation
          2. 8.4.3.2.2 Frequency Reduction
        3. 8.4.3.3 FPWM Mode - Light Load Operation
        4. 8.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 8.4.3.5 Dropout
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Choosing the Switching Frequency
        2. 9.2.2.2 Setting the Output Voltage
          1. 9.2.2.2.1 FB for Adjustable Output
        3. 9.2.2.3 Inductor Selection
        4. 9.2.2.4 Output Capacitor Selection
        5. 9.2.2.5 Input Capacitor Selection
        6. 9.2.2.6 CBOOT
        7. 9.2.2.7 VCC
        8. 9.2.2.8 CFF Selection
          1. 9.2.2.8.1 External UVLO
        9. 9.2.2.9 Maximum Ambient Temperature
      3. 9.2.3 Application Curves
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
        1. 9.5.1.1 Ground and Thermal Considerations
      2. 9.5.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VIN_R Minimum operating input voltage (rising) Rising threshold 3.4 3.5 V
VIN_F Minimum operating input voltage (falling) Once operating; Falling threshold 2.45 3.0 V
IQ_13p5_Fixed Non-switching input current; measured at VIN pin(2) VIN = VEN = 13.5V ; VOUT/BIAS = 5.25V, VRT = 0V; Fixed output 0.25 0.672 1.05 µA
IQ_13p5_Adj Non-switching input current; measured at VIN pin(2) VIN = VEN = 13.5V ; VFB = 1.05V, VRT = 0V; Adjustable output 14 17 22 µA
IQ_24p0_Fixed Non-switching input current; measured at VIN pin(2) VIN = VEN = 24V ; VOUT/BIAS = 5.25V, VRT = 0V; Fixed output 0.8 1.2 1.7 µA
IQ_24p0_Adj Non-switching input current; measured at VIN pin(2) VIN = VEN = 24V ; VFB = 1.05V, VRT = 0V; Adjustable output 14 18 22
µA
IB_13p5 Current into VOUT/BIAS pin (not switching)(2) VIN = 13.5V, VOUT/BIAS = 5.25V, VRT = 0V; Fixed output 14 17 22 µA
IB_24p0 Current into VOUT/BIAS pin (not switching)(2) VIN = 24V, VOUT/BIAS = 5.25V, VRT = 0V; Fixed output 14 18 22 µA
ISD_13p5 Shutdown quiescent current; measured at VIN pin(2) VEN = 0; VIN = 13.5V 0.5 1.1 µA
ISD_24p0 Shutdown quiescent current; measured at VIN pin(2) VEN = 0; VIN = 24V 1 1.6 µA
ENABLE (EN PIN)
VEN-WAKE Enable wake-up threshold 0.4 V
VEN-VOUT Precision enable high level for VOUT 1.16 1.263 1.36 V
VEN-HYST Enable threshold hysteresis below VEN-VOUT 0.3 0.35 0.4 V
ILKG-EN Enable input leakage current VEN = 3.3 V 0.3 8 nA
INTERNAL LDO
VCC Internal VCC voltage Adjustable or fixed  output;  Auto mode 3.125 3.15 3.22 V
ICC Bias regulator current limit 65 240 mA
VCC-UVLO Internal VCC undervoltage lockout VCC rising under voltage threshold 3 3.3 3.65 V
VCC-UVLO-HYST Internal VCC under voltage lock-out hysteresis Hysteresis below VCC-UVLO 0.4 0.8 1.2 V
CURRENT LIMITS
ISC-0p3 Short circuit high side current Limit(3) 0.3A Version 0.42 0.5 0.575 A
ILS-LIMIT-0p3 Low side current limit(3) 0.3A Version 0.3 0.35 0.4 A
IPEAK-MIN-0p3 Minimum peak inductor current(3) PFM Operation, 0.3A Version; Duty Factor = 0 0.067 0.09 0.11 A
ISC-0p6 Short circuit high side current Limit(3) 0.87 1 1.11 A
ILS-LIMIT-0p6 Low side current limit(3) 0.6 0.7 0.752 A
IPEAK-MIN-0p6 Minimum Peak Inductor Current(3) Auto Mode, duty factor = 0 0.127 0.19 0.227 A
IZC Zero cross current(3) Auto mode 0 0.01 0.022 A
IL-NEG Sink current limit (negative)(3) FPWM mode 0.6 0.7 0.8 A
POWER GOOD
PG-OV PGOOD upper threshold - rising % of FB (Adjustable output) or % of VOUT/BIAS (Fixed output) 106 107 110 %
PG-UV PGOOD lower threshold - falling % of FB (Adjustable output) or % of VOUT/BIAS (Fixed output) 93 94 96.5 %
PG-HYS PGOOD hysteresis - rising/falling  % of FB (Adjustable output) or % of VOUT/BIAS (Fixed output) 1.3 1.8 2.3 %
VPG-VALID Minimum input voltage for proper PG function 0.75 1 2 V
RPG-EN5p0 RDS(ON) PGOOD output VEN = 5.0V, 1mA pull-up current 20 40 70 Ω
RPG-EN0 RDS(ON) PGOOD output VEN = 0 V, 1mA pull-up current 10 18 31 Ω
MOSFETS
RDS-ON-HS High-side MOSFET on-resistance Load = 0.3 A 560 920 mΩ
RDS-ON-LS Low-side MOSFET on-resistance Load = 0.3 A 280 460 mΩ
VCBOOT-UVLO Cboot - SW UVLO threshold(4) 2.14 2.3 2.42 V
VOLTAGE REFERENCE
VOUT_Fixed3p3 Initial VOUT voltage accuracy for 3.3 V FPWM mode 3.25 3.3 3.34 V
VOUT_Fixed5p0 Initial VOUT voltage accuracy for 5 V FPWM mode 4.93 5 5.07 V
VREF Internal reference voltage VIN = 3.6V to 65V, FPWM mode 0.985 1 1.01 V
IFB FB input current Adjustable output, FB = 1V 85 110 nA
(1) MIN and MAX limits are 100% production tested at 25ºC. Limits over the operating temperature range verified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
(3) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.
(4) When the voltage across the CBOOT capacitor falls below this voltage, the low side MOSFET is turn to recharge the boot capacitor