SLOSEG0A November   2025  – November 2025 LOG305

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics Log Detector 
    6. 5.6 Typical Characteristics: VCC = 3.6V
    7. 5.7 Typical Characteristics: VCC = 5.25V
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Gain
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Energy Detection
        1. 8.2.1.1 Detailed Design Procedure
        2. 8.2.1.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • DRV|6
サーマルパッド・メカニカル・データ
発注情報

Layout Guidelines

Follow these instructions to improve the performance and noise immunity of the LOG305:

  • Design Log_In trace with guard traces to improve immunity against noise pickup. Use shielding when possible to improve radiated noise immunity.
  • Place small capacitors on the Log_En pin to allow high-frequency noise to be grounded before entering into the device.
  • Keep minimal capacitance at the Log_Out and FB pin either by placing the load circuit close to the pin or by removing the analog ground plane under the output trace or both. The Log_Out supports up to 100pF capacitance.
  • Dedicate one layer of the PCB for a solid analog ground pour to terminate all the capacitors used across the pins using sufficient vias.