JAJSG64C March   2015  – August 2018 LP8758-B0

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 概略回路図
    1.     効率と出力電流との関係(VIN = 3.7V)
  5. 5 改訂履歴
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Serial Bus Timing Parameter
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Buck Information
        1. 8.1.1.1 Operating Modes
        2. 8.1.1.2 Features
        3. 8.1.1.3 Programmability
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Multi-Phase DC-DC Converters
        1. 8.3.1.1 Overview
        2. 8.3.1.2 Multi-Phase Operation and Phase Adding/Shedding
        3. 8.3.1.3 Transition Between PWM and PFM Modes
        4. 8.3.1.4 Multi-Phase Switcher Configurations
        5. 8.3.1.5 Buck Converter Load Current Measurement
        6. 8.3.1.6 Spread-Spectrum Mode
      2. 8.3.2 Power-Up
      3. 8.3.3 Regulator Control
        1. 8.3.3.1 Enabling and Disabling Regulator
        2. 8.3.3.2 Changing Output Voltage
      4. 8.3.4 Device Reset Scenarios
      5. 8.3.5 Diagnosis and Protection Features
        1. 8.3.5.1 Warnings for Diagnosis (Interrupt)
          1. 8.3.5.1.1 Output Current Limit
          2. 8.3.5.1.2 Thermal Warning
        2. 8.3.5.2 Protection (Regulator Disable)
          1. 8.3.5.2.1 Short-Circuit and Overload Protection
          2. 8.3.5.2.2 Thermal Shutdown
        3. 8.3.5.3 Fault (Power Down)
          1. 8.3.5.3.1 Undervoltage Lockout
      6. 8.3.6 Digital Signal Filtering
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 Start and Stop Conditions
        3. 8.5.1.3 Transferring Data
        4. 8.5.1.4 I2C-Compatible Chip Address
        5. 8.5.1.5 Auto Increment Feature
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1  DEV_REV
        2. 8.6.1.2  OTP_REV
        3. 8.6.1.3  BUCK0_CTRL1
        4. 8.6.1.4  BUCK0_CTRL2
        5. 8.6.1.5  BUCK1_CTRL2
        6. 8.6.1.6  BUCK2_CTRL2
        7. 8.6.1.7  BUCK3_CTRL2
        8. 8.6.1.8  BUCK0_VOUT
        9. 8.6.1.9  BUCK0_FLOOR_VOUT
        10. 8.6.1.10 BUCK0_DELAY
        11. 8.6.1.11 RESET
        12. 8.6.1.12 CONFIG
        13. 8.6.1.13 INT_TOP
        14. 8.6.1.14 INT_BUCK_0_1
        15. 8.6.1.15 INT_BUCK_2_3
        16. 8.6.1.16 TOP_STAT
        17. 8.6.1.17 BUCK_0_1_STAT
        18. 8.6.1.18 BUCK_2_3_STAT
        19. 8.6.1.19 TOP_MASK
        20. 8.6.1.20 BUCK_0_1_MASK
        21. 8.6.1.21 BUCK_2_3_MASK
        22. 8.6.1.22 SEL_I_LOAD
        23. 8.6.1.23 I_LOAD_2
        24. 8.6.1.24 I_LOAD_1
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application Components
          1. 9.2.2.1.1 Inductor Selection
          2. 9.2.2.1.2 Input Capacitor Selection
          3. 9.2.2.1.3 Output Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.3.1 Enabling and Disabling Regulator

The regulator can be enabled when the device is in STANDBY state. There are two ways for enable and disable the regulator:

  • Using BUCK0_CTRL1.EN_BUCK0 register bit (BUCK0_CTRL1.EN_PIN_CTRL0 register bit is '0').
  • Using EN1/2 control pins (BUCK0_CTRL1.EN_BUCK0 register bit is '1' AND
    BUCK0_CTRL1.EN_PIN_CTRL0 register bit is '1').

If the EN1/2 control pins are used for enable and disable then the delay from the control signal rising edge to startup is set by BUCK0_DELAY.BUCK0_STARTUP_DELAY[3:0] bits and the delay from control signal falling edge to shutdown is set by BUCK0_DELAY.BUCK0_SHUTDOWN_DELAY[3:0] bits. The delays are valid only for EN1/2 signal and not for control with BUCK0_CTRL1.EN_BUCK0 bit. The delay time implemented by EN1/2 has overall +/-10% timing accuracy.

The control of the regulator (with 0 ms delays) is shown in Table 1. The multi-phase regulator is controlled with registers of the master phase.

Table 1. Regulator Control

CONTROL METHOD ROW EN_BUCKx0 BUCK0_CTRL1
EN_PIN_CTRL0		 BUCK0_CTRL1
EN_PIN_SELECT0		 BUCK0_CTRL1
EN_ROOF_FLOOR0		 EN1 PIN EN2 PIN BUCK0
OUTPUT VOLTAGE
Enable/disable control with EN_BUCK0 bit 1 0 Don't Care Don't Care Don't Care Don't Care Don't Care Disabled
2 1 0 Don't Care Don't Care Don't Care Don't Care BUCK0_VOUT.BUCK0_VSET[7:0]
Enable/disable control with EN1 pin 3 1 1 0 0 Low Don't Care Disabled
4 1 1 0 0 High Don't Care BUCK0_VOUT.BUCK0_VSET[7:0]
Enable/disable control with EN2 pin 5 1 1 1 0 Don't Care Low Disabled
6 1 1 1 0 Don't Care High BUCK0_VOUT.BUCK0_VSET[7:0]
Roof/floor control with EN1 pin 7 1 1 0 1 Low Don't Care BUCK0_FLOOR_VOUT.BUCK0_FLOOR_VSET[7:0]
8 1 1 0 1 High Don't Care BUCK0_VOUT.BUCK0_VSET[7:0]
Roof/floor control with EN2 pin 9 1 1 1 1 Don't Care Low BUCK0_FLOOR_VOUT.BUCK0_FLOOR_VSET[7:0]
10 1 1 1 1 Don't Care High BUCK0_VOUT.BUCK0_VSET[7:0]

The following configuration allows the enable/disable control using ENx pin:

  • BUCK0_CTRL1.EN_BUCK0 = 1
  • BUCK0_CTRL1.EN_PIN_CTRL0 = 1
  • BUCK0_CTRL1.EN_ROOF_FLOOR0 = 0
  • BUCK0_VOUT.BUCK0_VSET[7:0] = Required voltage when ENx is high
  • The enable pin for control is selected with BUCK0_CTRL1.EN_PIN_SELECT0

When the ENx pin is low, Table 1 row 3 (or 5) is valid, and the regulator is disabled. By setting ENx pin high, Table 1 row 4 (or 6) is valid, and the regulator is enabled with required voltage.

If the regulator is enabled all the time, and the ENx pin controls selection between two voltage level, the following configuration is used:

  • BUCK0_CTRL1.EN_BUCK0 = 1
  • BUCK0_CTRL1.EN_PIN_CTRL0 = 1
  • BUCK0_CTRL1.EN_ROOF_FLOOR0 = 1
  • BUCK0_VOUT.BUCK0_VSET[7:0] = Required voltage when ENx is high
  • The enable pin for control is selected with BUCK0_CTRL1.EN_PIN_SELECT0

When the ENx pin is low, Table 1 row 7(or 9) is valid, and the regulator is enabled with a voltage defined by BUCK0_FLOOR_VOUT.BUCK0_FLOOR_VSET[7:0] bits. Setting the ENx pin high, Table 1 row 8 (or 10) is valid, and the regulator is enabled with a voltage defined by BUCK0_VOUT.BUCK0_VSET[7:0] bits.

If the regulator is controlled by I2C writings, the BUCK0_CTRL1.EN_PIN_CTRL0 bit is set to 0. The enable/disable is controlled by the BUCK0_CTRL1.EN_BUCK0 bit, and when the regulator is enabled, the output voltage is defined by the BUCK0_VOUT.BUCK0_VSET[7:0] bits. The Table 1 rows 1 and 2 are valid for I2C controlled operation (ENx pins are ignored).

The regulator is enabled by the ENx pin or by I2C writing as shown in Figure 11. The soft-start circuit limits the in-rush current during start-up. Output voltage increase rate is around 30 mV/μsec during soft-start. When the output voltage rises to approximately 0.3 V, the output voltage becomes slew-rate controlled. If there is a short circuit at the output, and the output voltage does not increase above a 0.35-V level in 1 ms, the regulator is disabled, and interrupt is set. When the output voltage reaches the powergood threshold level the INT_BUCK_0_1.BUCK0_PG_INT interrupt flag is set. The powergood interrupt flag can be masked using BUCK_0_1_MASK.BUCK0_PG_MASK bit.

The ENx input pins have integrated pull-down resistors. The pull-down resistors are enabled by default and host can disable those with CONFIG.ENx_PD bits.

LP8758-B0 Enable_Disable_4ph.gifFigure 11. Regulator Enable and Disable