JAJSG64C March   2015  – August 2018 LP8758-B0

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 概略回路図
    1.     効率と出力電流との関係(VIN = 3.7V)
  5. 5 改訂履歴
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Serial Bus Timing Parameter
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Buck Information
        1. 8.1.1.1 Operating Modes
        2. 8.1.1.2 Features
        3. 8.1.1.3 Programmability
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Multi-Phase DC-DC Converters
        1. 8.3.1.1 Overview
        2. 8.3.1.2 Multi-Phase Operation and Phase Adding/Shedding
        3. 8.3.1.3 Transition Between PWM and PFM Modes
        4. 8.3.1.4 Multi-Phase Switcher Configurations
        5. 8.3.1.5 Buck Converter Load Current Measurement
        6. 8.3.1.6 Spread-Spectrum Mode
      2. 8.3.2 Power-Up
      3. 8.3.3 Regulator Control
        1. 8.3.3.1 Enabling and Disabling Regulator
        2. 8.3.3.2 Changing Output Voltage
      4. 8.3.4 Device Reset Scenarios
      5. 8.3.5 Diagnosis and Protection Features
        1. 8.3.5.1 Warnings for Diagnosis (Interrupt)
          1. 8.3.5.1.1 Output Current Limit
          2. 8.3.5.1.2 Thermal Warning
        2. 8.3.5.2 Protection (Regulator Disable)
          1. 8.3.5.2.1 Short-Circuit and Overload Protection
          2. 8.3.5.2.2 Thermal Shutdown
        3. 8.3.5.3 Fault (Power Down)
          1. 8.3.5.3.1 Undervoltage Lockout
      6. 8.3.6 Digital Signal Filtering
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 Start and Stop Conditions
        3. 8.5.1.3 Transferring Data
        4. 8.5.1.4 I2C-Compatible Chip Address
        5. 8.5.1.5 Auto Increment Feature
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1  DEV_REV
        2. 8.6.1.2  OTP_REV
        3. 8.6.1.3  BUCK0_CTRL1
        4. 8.6.1.4  BUCK0_CTRL2
        5. 8.6.1.5  BUCK1_CTRL2
        6. 8.6.1.6  BUCK2_CTRL2
        7. 8.6.1.7  BUCK3_CTRL2
        8. 8.6.1.8  BUCK0_VOUT
        9. 8.6.1.9  BUCK0_FLOOR_VOUT
        10. 8.6.1.10 BUCK0_DELAY
        11. 8.6.1.11 RESET
        12. 8.6.1.12 CONFIG
        13. 8.6.1.13 INT_TOP
        14. 8.6.1.14 INT_BUCK_0_1
        15. 8.6.1.15 INT_BUCK_2_3
        16. 8.6.1.16 TOP_STAT
        17. 8.6.1.17 BUCK_0_1_STAT
        18. 8.6.1.18 BUCK_2_3_STAT
        19. 8.6.1.19 TOP_MASK
        20. 8.6.1.20 BUCK_0_1_MASK
        21. 8.6.1.21 BUCK_2_3_MASK
        22. 8.6.1.22 SEL_I_LOAD
        23. 8.6.1.23 I_LOAD_2
        24. 8.6.1.24 I_LOAD_1
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application Components
          1. 9.2.2.1.1 Inductor Selection
          2. 9.2.2.1.2 Input Capacitor Selection
          3. 9.2.2.1.3 Output Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

YFF Package
35-Pin DSBGA
LP8758-B0 Ballmap_58.gif

Pin Functions

PIN TYPE DESCRIPTION
NUMBER NAME
A1, B1 VIN_B1 P Input for Buck 1. The separate power pins VIN_Bx are not connected together internally - VIN_Bx pins must be connected together in the application and be locally bypassed.
A2, B2 SW_B1 A Buck 1 switch node.
A3, B3, C3 PGND_B01 G Power Ground for Buck 0 and Buck 1.
A4, B4 SW_B0 A Buck 0 switch node.
A5, B5 VIN_B0 P Input for Buck 0. The separate power pins VIN_Bx are not connected together internally - VIN_Bx pins must be connected together in the application and be locally bypassed.
C1 SGND G Substrate Ground.
C2 FB_B1 A Output ground feedback (negative) for Buck 0.
C4 FB_B0 A Output voltage feedback (positive) for Buck 0.
C5 EN1 D/I Programmable Enable signal for Buck regulator. Can be also configured to switch between two output voltage levels.
D1 AGND G Ground.
D2 nINT D/O Open-drain interrupt output. Active LOW.
D3 EN2 D/I Programmable Enable signal for Buck regulator. Can be also configured to switch between two output voltage levels.
D4 NRST D/I Reset signal for the device.
D5 SDA D/I/O Serial interface data input and output for system access. Connect a pull-up resistor.
E1 VANA P Supply voltage for Analog and Digital blocks. VANA pin must be connected to same voltage as VIN_Bx pins.
E2 FB_B3 A Output voltage feedback (positive) for Buck 3 - Connect to ground in 4-phase configuration.
E4 FB_B2 A Output voltage feedback (positive) for Buck 2. - Connect to ground in 4-phase configuration.
E5 SCL D/I Serial interface clock input for system access. Connect a pull-up resistor.
F1, G1 VIN_B3 P Input for Buck 3. The separate power pins VIN_Bx are not connected together internally - VIN_Bx pins must be connected together in the application and be locally bypassed.
F2, G2 SW_B3 A Buck 3 switch node.
E3, F3, G3 PGND_B23 G Power Ground for Buck 2 and Buck 3.
F4, G4 SW_B2 A Buck 2 switch node.
F5, G5 VIN_B2 P Input for Buck 2. The separate power pins VIN_Bx are not connected together internally - VIN_Bx pins must be connected together in the application and be locally bypassed.
A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin