JAJSG64C March   2015  – August 2018 LP8758-B0

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 概略回路図
    1.     効率と出力電流との関係(VIN = 3.7V)
  5. 5 改訂履歴
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Serial Bus Timing Parameter
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Buck Information
        1. 8.1.1.1 Operating Modes
        2. 8.1.1.2 Features
        3. 8.1.1.3 Programmability
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Multi-Phase DC-DC Converters
        1. 8.3.1.1 Overview
        2. 8.3.1.2 Multi-Phase Operation and Phase Adding/Shedding
        3. 8.3.1.3 Transition Between PWM and PFM Modes
        4. 8.3.1.4 Multi-Phase Switcher Configurations
        5. 8.3.1.5 Buck Converter Load Current Measurement
        6. 8.3.1.6 Spread-Spectrum Mode
      2. 8.3.2 Power-Up
      3. 8.3.3 Regulator Control
        1. 8.3.3.1 Enabling and Disabling Regulator
        2. 8.3.3.2 Changing Output Voltage
      4. 8.3.4 Device Reset Scenarios
      5. 8.3.5 Diagnosis and Protection Features
        1. 8.3.5.1 Warnings for Diagnosis (Interrupt)
          1. 8.3.5.1.1 Output Current Limit
          2. 8.3.5.1.2 Thermal Warning
        2. 8.3.5.2 Protection (Regulator Disable)
          1. 8.3.5.2.1 Short-Circuit and Overload Protection
          2. 8.3.5.2.2 Thermal Shutdown
        3. 8.3.5.3 Fault (Power Down)
          1. 8.3.5.3.1 Undervoltage Lockout
      6. 8.3.6 Digital Signal Filtering
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 Start and Stop Conditions
        3. 8.5.1.3 Transferring Data
        4. 8.5.1.4 I2C-Compatible Chip Address
        5. 8.5.1.5 Auto Increment Feature
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1  DEV_REV
        2. 8.6.1.2  OTP_REV
        3. 8.6.1.3  BUCK0_CTRL1
        4. 8.6.1.4  BUCK0_CTRL2
        5. 8.6.1.5  BUCK1_CTRL2
        6. 8.6.1.6  BUCK2_CTRL2
        7. 8.6.1.7  BUCK3_CTRL2
        8. 8.6.1.8  BUCK0_VOUT
        9. 8.6.1.9  BUCK0_FLOOR_VOUT
        10. 8.6.1.10 BUCK0_DELAY
        11. 8.6.1.11 RESET
        12. 8.6.1.12 CONFIG
        13. 8.6.1.13 INT_TOP
        14. 8.6.1.14 INT_BUCK_0_1
        15. 8.6.1.15 INT_BUCK_2_3
        16. 8.6.1.16 TOP_STAT
        17. 8.6.1.17 BUCK_0_1_STAT
        18. 8.6.1.18 BUCK_2_3_STAT
        19. 8.6.1.19 TOP_MASK
        20. 8.6.1.20 BUCK_0_1_MASK
        21. 8.6.1.21 BUCK_2_3_MASK
        22. 8.6.1.22 SEL_I_LOAD
        23. 8.6.1.23 I_LOAD_2
        24. 8.6.1.24 I_LOAD_1
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application Components
          1. 9.2.2.1.1 Inductor Selection
          2. 9.2.2.1.2 Input Capacitor Selection
          3. 9.2.2.1.3 Output Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.6.1 Register Descriptions

The LP8758 is controlled by a set of registers through the system serial interface port. The device registers, their addresses and their abbreviations are listed in Table 5. A more detailed description is given in sections DEV_REV to I_LOAD_1.

Table 5. Summary of LP8758 Control Registers

Addr Register Read / Write D7 D6 D5 D4 D3 D2 D1 D0
0x01 OTP_REV R OTP_ID[7:0]
0x02 BUCK0_
CTRL1		 R/W EN_BUCK0 EN_PIN_
CTRL0		 EN_PIN_
SELECT0		 EN_ROOF
_FLOOR0		 EN_RDIS0 Reserved BUCK0_
FPWM		 BUCK0
_FPWM
_MP
0x03 BUCK0_
CTRL2		 R/W Reserved ILIM0[2:0] SLEW_RATE0[2:0]
0x05 BUCK1_
CTRL2		 R/W Reserved ILIM1[2:0] Reserved
0x07 BUCK2_
CTRL2		 R/W Reserved ILIM2[2:0] Reserved
0x09 BUCK3_
CTRL2		 R/W Reserved ILIM3[2:0] Reserved
0x0A BUCK0_
VOUT		 R/W BUCK0_VSET[7:0]
0x0B BUCK0_
FLOOR_
VOUT		 R/W BUCK0_FLOOR_VSET[7:0]
0x12 BUCK0_
DELAY		 R/W BUCK0_SHUTDOWN_DELAY[3:0] BUCK0_STARTUP_DELAY[3:0]
0x16 RESET R/W Reserved SW_
RESET
0x17 CONFIG R/W Reserved TDIE
_WARN
_LEVEL		 EN2_PD EN1_PD EN_
SPREAD
_SPEC
0x18 INT_TOP R/W INT_
BUCK3		 INT_
BUCK2		 INT_
BUCK1		 INT_
BUCK0		 TDIE_SD TDIE_
WARN		 RESET_
REG		 I_LOAD_
READY
0x19 INT_BUCK_0_1 R/W Reserved BUCK1_
ILIM_INT		 Reserved BUCK0_
PG_INT		 BUCK0_
SC_INT		 BUCK0_
ILIM_INT
0x1A INT_BUCK_2_3 R/W Reserved BUCK3_
ILIM_INT		 Reserved BUCK2_
ILIM_INT
0x1B TOP_
STAT		 R Reserved TDIE_SD
_STAT		 TDIE_
WARN_
STAT		 Reserved
0x1C BUCK_0_1_STAT R Reserved BUCK1_
ILIM_
STAT		 BUCK0_
STAT		 BUCK0_
PG_STAT		 Reserved BUCK0_
ILIM_
STAT
0x1D BUCK_2_3_STAT R Reserved BUCK3_
ILIM_STAT		 Reserved BUCK2_
ILIM_STAT
0x1E TOP_
MASK		 R/W Reserved TDIE_WARN_MASK RESET_
REG_MASK		 I_LOAD_
READY_
MASK
0x1F BUCK_0_1_MASK R/W Reserved BUCK1_
ILIM_
MASK		 Reserved BUCK0_
PG_MASK		 Reserved BUCK0_
ILIM_
MASK
0x20 BUCK_2_3_MASK R/W Reserved BUCK3_
ILIM_
MASK		 Reserved BUCK2_
ILIM_
MASK
0x21 SEL_I_
LOAD		 R/W Reserved LOAD_CURRENT_
BUCK_SELECT[1:0]
0x22 I_LOAD_2 R/W Reserved BUCK_LOAD_CURRENT[9:8]
0x23 I_LOAD_1 R/W BUCK_LOAD_CURRENT[7:0]