JAJSMS0C august   2021  – june 2023 MCF8316A

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Device Interface Modes
        1. 7.3.2.1 Interface - Control and Monitoring
        2. 7.3.2.2 I2C Interface
      3. 7.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 7.3.3.1 Buck in Inductor Mode
        2. 7.3.3.2 Buck in Resistor mode
        3. 7.3.3.3 Buck Regulator with External LDO
        4. 7.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 7.3.3.5 Mixed Mode Buck Operation and Control
        6. 7.3.3.6 Buck Undervoltage Protection
        7. 7.3.3.7 Buck Overcurrent Protection
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  SPEED Control
        1. 7.3.8.1 Analog-Mode Speed Control
        2. 7.3.8.2 PWM-Mode Speed Control
        3. 7.3.8.3 I2C based Speed Control
        4. 7.3.8.4 Frequency-Mode Speed Control
        5. 7.3.8.5 Speed Profiles
          1. 7.3.8.5.1 Linear Speed Profiles
          2. 7.3.8.5.2 Staircase Speed Profiles
          3. 7.3.8.5.3 Forward-Reverse Speed Profiles
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
          1. 7.3.10.3.1 Reverse Drive Tuning
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release Mode
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 Closed Loop Acceleration/Deceleration Slew Rate
        2. 7.3.11.2 Speed PI Control
        3. 7.3.11.3 Current PI Control
        4. 7.3.11.4 Overmodulation
      12. 7.3.12 Motor Parameters
        1. 7.3.12.1 Motor Resistance
        2. 7.3.12.2 Motor Inductance
        3. 7.3.12.3 Motor Back-EMF constant
      13. 7.3.13 Motor Parameter Extraction Tool (MPET)
      14. 7.3.14 Anti-Voltage Surge (AVS)
      15. 7.3.15 Output PWM Switching Frequency
      16. 7.3.16 Active Braking
      17. 7.3.17 PWM Modulation Schemes
      18. 7.3.18 Dead Time Compensation
      19. 7.3.19 Motor Stop Options
        1. 7.3.19.1 Coast (Hi-Z) Mode
        2. 7.3.19.2 Recirculation Mode
        3. 7.3.19.3 Low-Side Braking
        4. 7.3.19.4 High-Side Braking
        5. 7.3.19.5 Active Spin-Down
        6. 7.3.19.6 Align Braking
      20. 7.3.20 FG Configuration
        1. 7.3.20.1 FG Output Frequency
        2. 7.3.20.2 FG Open-Loop and Lock Behavior
      21. 7.3.21 DC Bus Current Limit
      22. 7.3.22 Protections
        1. 7.3.22.1  VM Supply Undervoltage Lockout
        2. 7.3.22.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 7.3.22.3  BUCK Undervoltage Lockout (BUCK_UV)
        4. 7.3.22.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.22.5  Overvoltage Protection (OVP)
        6. 7.3.22.6  Overcurrent Protection (OCP)
          1. 7.3.22.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.22.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 7.3.22.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 7.3.22.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 7.3.22.7  Buck Overcurrent Protection
        8. 7.3.22.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.22.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.22.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.22.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.22.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1xx1b)
        9. 7.3.22.9  Thermal Warning (OTW)
        10. 7.3.22.10 Thermal Shutdown (TSD)
        11. 7.3.22.11 Motor Lock (MTR_LCK)
          1. 7.3.22.11.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.22.11.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.22.11.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.22.11.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        12. 7.3.22.12 Motor Lock Detection
          1. 7.3.22.12.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.22.12.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.22.12.3 Lock3: No-Motor Fault (NO_MTR)
        13. 7.3.22.13 MPET Faults
        14. 7.3.22.14 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF Functionality
      2. 7.5.2 SOX Output
      3. 7.5.3 Oscillator Source
        1. 7.5.3.1 External Clock Source
      4. 7.5.4 External Watchdog
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Operation
        3. 7.6.2.3 I2C Read Operation
        4. 7.6.2.4 Examples of MCF8316A I2C Communication Protocol Packets
        5. 7.6.2.5 Internal Buffers
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Fault_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Internal_Algorithm_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 System_Status Registers
      3. 7.8.3 Device_Control Registers
      4. 7.8.4 Algorithm_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application Curves
        1. 8.2.1.1 Motor startup
        2. 8.2.1.2 MPET
        3. 8.2.1.3 Dead time compensation
        4. 8.2.1.4 Auto handoff
        5. 8.2.1.5 Motor stop – recirculation mode
        6. 8.2.1.6 Anti voltage surge (AVS)
  10. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 サポート・リソース
    2. 11.2 Trademarks
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.7.3 Hardware_Configuration Registers

HARDWARE_CONFIGURATION Registers lists the memory-mapped registers for the Hardware_Configuration registers. All register offset addresses not listed in HARDWARE_CONFIGURATION Registers should be considered as reserved locations and the register contents should not be modified.

Table 7-33 HARDWARE_CONFIGURATION Registers
AddressAcronymRegister NameSection
A4hPIN_CONFIGHardware Pin ConfigurationPIN_CONFIG Register (Address = A4h) [Reset = 00000000h]
A6hDEVICE_CONFIG1Device Configuration 1DEVICE_CONFIG1 Register (Address = A6h) [Reset = X]
A8hDEVICE_CONFIG2Device Configuration 2DEVICE_CONFIG2 Register (Address = A8h) [Reset = 00000000h]
AAhPERI_CONFIG1Peripheral Configuration 1PERI_CONFIG1 Register (Address = AAh) [Reset = 40000000h]
AChGD_CONFIG1Gate Driver Configuration 1GD_CONFIG1 Register (Address = ACh) [Reset = 10228100h]
AEhGD_CONFIG2Gate Driver Configuration 2GD_CONFIG2 Register (Address = AEh) [Reset = 01200000h]

Complex bit access types are encoded to fit into small table cells. Hardware_Configuration Access Type Codes shows the codes that are used for access types in this section.

Table 7-34 Hardware_Configuration Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value

7.7.3.1 PIN_CONFIG Register (Address = A4h) [Reset = 00000000h]

PIN_CONFIG is shown in PIN_CONFIG Register and described in PIN_CONFIG Register Field Descriptions.

Return to the Summary Table.

Register to configure hardware pins

Figure 7-71 PIN_CONFIG Register
3130292827262524
PARITYRESERVED
R/W-0hR/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDBRAKE_PIN_MODEALIGN_BRAKE_ANGLE_SELBRAKE_INPUTSPEED_MODE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-35 PIN_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-6RESERVEDR/W0h Reserved
5BRAKE_PIN_MODER/W0h Brake pin mode

0h = Low side Brake

1h = Align Brake

4ALIGN_BRAKE_ANGLE_SELR/W0h Align brake angle select

0h = Use last commutation angle before entering align braking

1h = Use ALIGN_ANGLE configuration for align braking

3-2BRAKE_INPUTR/W0h Brake pin override

0h = Hardware Pin BRAKE

1h = Override pin and brake / align according to BRAKE_PIN_MODE

2h = Override pin and do not brake / align

3h = Hardware Pin BRAKE

1-0SPEED_MODER/W0h Configure speed control mode from speed pin

0h = Analog Mode

1h = Controlled by Duty Cycle of SPEED Input Pin

2h = Register Override mode

3h = Controlled by Frequency of SPEED Input Pin

7.7.3.2 DEVICE_CONFIG1 Register (Address = A6h) [Reset = X]

DEVICE_CONFIG1 is shown in DEVICE_CONFIG1 Register and described in DEVICE_CONFIG1 Register Field Descriptions.

Return to the Summary Table.

Register to configure device

Figure 7-72 DEVICE_CONFIG1 Register
3130292827262524
PARITYRESERVEDPIN_38_CONFIGRESERVEDI2C_TARGET_ADDR
R/W-0hR/W-0hR/W-0hR/W-0hR/W-X
2322212019181716
I2C_TARGET_ADDRRESERVED
R/W-XR/W-X
15141312111098
RESERVED
R/W-X
76543210
RESERVEDRESERVEDBUS_VOLT
R/W-XR/W-0hR/W-0h
Table 7-36 DEVICE_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30RESERVEDR/W0h Reserved
29-28PIN_38_CONFIGR/W0h Pin 38 configuration

0h = N/A

1h = SOA

2h = SOB

3h = SOC

27RESERVEDR/W0h Reserved
26-20I2C_TARGET_ADDRR/WX I2C target address
19-5RESERVEDR/WX Reserved
4-2RESERVEDR/W0h Reserved
1-0BUS_VOLTR/W0h Maximum bus voltage configuration

0h = 15 V

1h = 30 V

2h = 60 V

3h = Not defined

7.7.3.3 DEVICE_CONFIG2 Register (Address = A8h) [Reset = 00000000h]

DEVICE_CONFIG2 is shown in DEVICE_CONFIG2 Register and described in DEVICE_CONFIG2 Register Field Descriptions.

Return to the Summary Table.

Register to configure device

Figure 7-73 DEVICE_CONFIG2 Register
3130292827262524
PARITYINPUT_MAXIMUM_FREQ
R/W-0hR/W-0h
2322212019181716
INPUT_MAXIMUM_FREQ
R/W-0h
15141312111098
SLEEP_ENTRY_TIMEDYNAMIC_CSA_GAIN_ENDYNAMIC_VOLTAGE_GAIN_ENDEV_MODECLK_SELEXT_CLK_EN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
EXT_CLK_CONFIGEXT_WD_ENEXT_WD_CONFIGEXT_WD_INPUTEXT_WD_FAULT
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-37 DEVICE_CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-16INPUT_MAXIMUM_FREQR/W0h Input frequency on speed pin for speed control mode as "controlled by frequency speed pin input" that corresponds to 100% duty cycle. Input duty cycle = Input frequency / INPUT_MAXIMUM_FREQ
15-14SLEEP_ENTRY_TIMER/W0h Device enters sleep mode when speed input is held continuously below the speed threshold for SLEEP_ENTRY_TIME

0h = 50 µs

1h = 200 µs

2h = 20 ms

3h = 200 ms

13DYNAMIC_CSA_GAIN_ENR/W0h Adjust CSA gain at 1ms rate for optimal current resolution at all current levels

0h = Disable

1h = Enable

12DYNAMIC_VOLTAGE_GAIN_ENR/W0h Adjust voltage gain at 1ms rate for optimal voltage resolution at all voltage levels

0h = Dynamic Voltage Gain is Disabled

1h = Dynamic Voltage Gain is Enabled

11DEV_MODER/W0h Device mode select

0h = Standby Mode

1h = Sleep Mode

10-9CLK_SELR/W0h Clock source

0h = Internal Oscillator

1h = N/A

2h = N/A

3h = External Clock input

8EXT_CLK_ENR/W0h External clock mode enable

0h = Disable

1h = Enable

7-5EXT_CLK_CONFIGR/W0h External clock configuration

0h = 8 kHz

1h = 16 kHz

2h = 32 kHz

3h = 64 kHz

4h = 128 kHz

5h = 256 kHz

6h = 512 kHz

7h = 1024 kHz

4EXT_WD_ENR/W0h External watchdog enable

0h = Disable

1h = Enable

3-2EXT_WD_CONFIGR/W0h Time between watchdog tickles

0h = 100ms if GPIO mode; 1s if I2C mode

1h = 200ms if GPIO mode; 2s if I2C mode

2h = 500ms if GPIO mode; 5s if I2C mode

3h = 1000ms if GPIO mode; 10s if I2C mode

1EXT_WD_INPUTR/W0h External watchdog input mode

0h = Watchdog tickle over I2C

1h = Watchdog tickle over GPIO

0EXT_WD_FAULTR/W0h External watchdog fault mode

0h = Report Only

1h = Latch with Hi-Z outputs

7.7.3.4 PERI_CONFIG1 Register (Address = AAh) [Reset = 40000000h]

PERI_CONFIG1 is shown in PERI_CONFIG1 Register and described in PERI_CONFIG1 Register Field Descriptions.

Return to the Summary Table.

Register to peripheral1

Figure 7-74 PERI_CONFIG1 Register
3130292827262524
PARITYSPREAD_SPECTRUM_MODULATION_DISRESERVEDBUS_CURRENT_LIMIT
R/W-0hR/W-1hR/W-0hR/W-0h
2322212019181716
BUS_CURRENT_LIMITBUS_CURRENT_LIMIT_ENABLEDIR_INPUTDIR_CHANGE_MODESELF_TEST_ENABLEACTIVE_BRAKE_SPEED_DELTA_LIMIT
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
ACTIVE_BRAKE_SPEED_DELTA_LIMITACTIVE_BRAKE_MOD_INDEX_LIMITSPEED_RANGE_SELALARM_PIN_DIS
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVED
R/W-0h
Table 7-38 PERI_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30SPREAD_SPECTRUM_MODULATION_DISR/W1h Spread spectrum modulation disable

0h = SSM is Enabled

1h = SSM is Disabled

29-26RESERVEDR/W0h Reserved
25-22BUS_CURRENT_LIMITR/W0h Bus current limit

0h = 0.125 A

1h = 0.25 A

2h = 0.5 A

3h = 1.0 A

4h = 1.5 A

5h = 2.0 A

6h = 2.5 A

7h = 3.0 A

8h = 3.5 A

9h = 4.0 A

Ah = 4.5 A

Bh = 5.0 A

Ch = 5.5 A

Dh = 6.0 A

Eh = 7.0 A

Fh = 8.0 A

21BUS_CURRENT_LIMIT_ENABLER/W0h Bus current limit enable

0h = Disable

1h = Enable

20-19DIR_INPUTR/W0h DIR pin override

0h = Hardware Pin DIR

1h = Override DIR pin with clockwise rotation OUTA-OUTB-OUTC

2h = Override DIR pin with counter clockwise rotation OUTA-OUTC-OUTB

3h = Hardware Pin DIR

18DIR_CHANGE_MODER/W0h Response to change of DIR pin status

0h = Follow motor stop options and ISD routine on detecting DIR change

1h = Change the direction through Reverse Drive while continuously driving the motor

17SELF_TEST_ENABLER/W0h Self-test on power up enable

0h = STL is disabled

1h = STL is enabled

16-13ACTIVE_BRAKE_SPEED_DELTA_LIMITR/W0h Difference between final speed and present speed beyond which active braking will be applied

0h = 2.5%

1h = 5%

2h = 10%

3h = 15%

4h = 20%

5h = 25%

6h = 30%

7h = 35%

8h = 40%

9h = 45%

Ah = 50%

Bh = 60%

Ch = 70%

Dh = 80%

Eh = 90%

Fh = 100%

12-10ACTIVE_BRAKE_MOD_INDEX_LIMITR/W0h Modulation index limit beyond which active braking will be applied

0h = 0%

1h = 40%

2h = 50%

3h = 60%

4h = 70%

5h = 80%

6h = 90%

7h = 100%

9SPEED_RANGE_SELR/W0h Speed range selection for digital speed (PWM duty or frequency to speed mode)

0h = 325 Hz to 95 kHz

1h = 10 Hz to 325 Hz

8ALARM_PIN_DISR/W0h Alarm pin disable

0h = Alarm pin is enabled

1h = Alarm pin is disabled

7-0RESERVEDR/W0h Reserved

7.7.3.5 GD_CONFIG1 Register (Address = ACh) [Reset = 10228100h]

GD_CONFIG1 is shown in GD_CONFIG1 Register and described in GD_CONFIG1 Register Field Descriptions.

Return to the Summary Table.

Register to configure gated driver settings1

Figure 7-75 GD_CONFIG1 Register
3130292827262524
PARITYRESERVEDRESERVEDSLEW_RATERESERVED
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDOVP_SELOVP_ENRESERVEDOTW_REP
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1hR/W-0h
15141312111098
RESERVEDRESERVEDOCP_DEGTRETRYOCP_LVLOCP_MODE
R/W-1hR/W-0hR/W-0hR/W-0hR/W-0hR/W-1h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCSA_GAIN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-39 GD_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-29RESERVEDR/W0h Reserved
28RESERVEDR/W1h Reserved
27-26SLEW_RATER/W0h Slew rate

0h = Slew rate is 25 V/µs

1h = Slew rate is 50 V/µs

2h = Slew rate is 150 V/µs

3h = Slew rate is 200 V/µs

25-24RESERVEDR/W0h Reserved
23RESERVEDR/W0h Reserved
22RESERVEDR/W0h Reserved
21RESERVEDR/W1h Reserved
20RESERVEDR/W0h Reserved
19OVP_SELR/W0h Overvoltage protection level

0h = VM overvoltage level is 32-V

1h = VM overvoltage level is 20-V

18OVP_ENR/W0h Overvoltage protection enable

0h = Overvoltage protection is disabled

1h = Overvoltage protection is enabled

17RESERVEDR/W1h Reserved
16OTW_REPR/W0h Overtemperature warning reporting on nFAULT

0h = Over temperature reporting on nFAULT is disabled

1h = Over temperature reporting on nFAULT is enabled

15RESERVEDR/W1h Reserved
14RESERVEDR/W0h Reserved
13-12OCP_DEGR/W0h OCP deglitch time

0h = OCP deglitch time is 0.2 µs

1h = OCP deglitch time is 0.6 µs

2h = OCP deglitch time is 1.1 µs

3h = OCP deglitch time is 1.6 µs

11TRETRYR/W0h OCP retry time

0h = OCP retry time is 5 ms

1h = OCP retry time is 500 ms

10OCP_LVLR/W0h OCP level

0h = OCP level is 16 A (Typical)

1h = OCP level is 24 A (Typical)

9-8OCP_MODER/W1h OCP fault mode

0h = Overcurrent causes a latched fault

1h = Overcurrent causes an automatic retrying fault

2h = Overcurrent is report only but no action is taken

3h = Overcurrent is not reported and no action is taken

7RESERVEDR/W0h Reserved
6RESERVEDR/W0h Reserved
5RESERVEDR/W0h Reserved
4RESERVEDR/W0h Reserved
3RESERVEDR/W0h Reserved
2RESERVEDR/W0h Reserved
1-0CSA_GAINR/W0h Current Sense Amplifier (CSA) gain (used only if DYNAMIC_CSA_GAIN_EN = 0)

0h = CSA gain is 0.15 V/A

1h = CSA gain is 0.3 V/A

2h = CSA gain is 0.6 V/A

3h = CSA gain is 1.2 V/A

7.7.3.6 GD_CONFIG2 Register (Address = AEh) [Reset = 01200000h]

GD_CONFIG2 is shown in GD_CONFIG2 Register and described in GD_CONFIG2 Register Field Descriptions.

Return to the Summary Table.

Register to configure gated driver settings2

Figure 7-76 GD_CONFIG2 Register
3130292827262524
PARITYDELAY_COMP_ENTARGET_DELAYBUCK_SRBUCK_PS_DIS
R/W-0hR/W-0hR/W-0hR/W-0hR/W1C-1h
2322212019181716
BUCK_CLBUCK_SELBUCK_DISRESERVED
R/W-0hR/W-1hR/W-0hR/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVED
R/W-0h
Table 7-40 GD_CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30DELAY_COMP_ENR/W0h Driver delay compensation enable

0h = Disable

1h = Enable

29-26TARGET_DELAYR/W0h Target delay

0h = Automatic based on slew rate

1h = 0.4 µs

2h = 0.6 µs

3h = 0.8 µs

4h = 1 µs

5h = 1.2 µs

6h = 1.4 µs

7h = 1.6 µs

8h = 1.8 µs

9h = 2 µs

Ah = 2.2 µs

Bh = 2.4 µs

Ch = 2.6 µs

Dh = 2.8 µs

Eh = 3 µs

Fh = 3.2 µs

25BUCK_SRR/W0h Buck slew rate

0h = Buck's FET slew rate is 1000V/µs

1h = Buck's FET slew rate is 200V/µs

24BUCK_PS_DISR/W1C1h Buck power sequencing disable

0h = Buck power sequencing is enabled

1h = Buck power sequencing is disabled

23BUCK_CLR/W0h Buck current limit

0h = Buck regulator current limit is set to 600 mA

1h = Buck regulator current limit is set to 150 mA

22-21BUCK_SELR/W1h Buck voltage selection

0h = Buck voltage is 3.3 V

1h = Buck voltage is 5.0 V

2h = Buck voltage is 4.0 V

3h = Buck voltage is 5.7 V

20BUCK_DISR/W0h Buck disable

0h = Buck regulator is enabled

1h = Buck regulator is disabled

19-0RESERVEDR/W0h Reserved