JAJSMD4D December   2003  – March 2022 OPA1632

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: OPA1632D
    6. 6.6 Electrical Characteristics: OPA1632DGN
    7. 6.7 Typical Characteristics: OPA1632D
    8. 6.8 Typical Characteristics: OPA1632DGN
  7. Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Fully-Differential Amplifiers
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Function
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Output Common-Mode Voltage
        1. 8.1.1.1 Resistor Matching
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PowerPAD Design Considerations
      2. 10.1.2 Power Dissipation and Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Third-Party Products Disclaimer
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Export Control Notice
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Electrical Characteristics: OPA1632D

VS = ±15 V; RF = 390 Ω, RL = 800 Ω, and G = +1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Offset Voltage
Input Offset Voltage ±0.5 ±3 mV
vs temperature, dc
dVOS/dT ±2.5 μV/°C
vs Power Supply, dc PSRR 13 316 μV/V
Input Bias Current
Input Bias Current IB 7.9 14 μA
Input Offset Current IOS ±100 ±500 nA
Noise
Input Voltage Noise f = 10 kHz 1.25 nV/√Hz
Input Current Noise f = 10 kHz 1.7 pA/√Hz
Input Voltage
Common-Mode Input Range (V−) + 1.5 (V+) − 1 V
Common-Mode Rejection Ratio, dc 74 90 dB
Input Impedance
Input Impedance
Measured into each input terminal, common-mode

215 || 1.4 MΩ || pF
Measured into each input terminal, differential 10 || 3.1 kΩ || pF
Open-Loop Gain
Open-Loop Gain, dc 66 78 dB
Frequency Response
Small-Signal Bandwidth G = +1, RF= 348 Ω 180 MHz
(VO = 100mVPP, Peaking < 0.5 dB) G = +2, RF = 602 Ω 104
G = +5, RF = 1.5 kΩ 46
G = +10, RF = 3.01 kΩ 24
Bandwidth for 0.1dB Flatness G = +1, VO = 100 mVPP 40 MHz
Peaking at a Gain of 1 VO = 100 mVPP 0.5 dB
Large-Signal Bandwidth G = +2, VO = 20 VPP 1.8 MHz
Slew Rate (25% to 75% ) G = +1 72 V/μs
Rise and Fall Time G = +1, VO = 5-V Step
69 ns
Settling Time to 0.1% G = +1, VO = 2-V Step 36 ns
0.01% 49 ns
Total Harmonic Distortion + Noise
Differential Input/Output G = +1, f = 1 kHz, VO = 3 VRMS RL = 600 Ω 0.00003%
RL = 2 kΩ 0.000028%
Single-Ended In/Differential Out RL = 600 Ω 0.000036%
RL = 2 kΩ 0.000031%
Intermodulation Distortion Differential Input/Output G = +1, SMPTE/DIN, VO = 2 VPP RL = 600 Ω 0.000061%
RL = 2 kΩ 0.000061%
Single-Ended In/Differential Out RL = 600 Ω 0.000073%
RL = 2 kΩ 0.00007%
Headroom THD < 0.01%, RL = 2 kΩ 20 VPP
Output
Voltage Output Swing Low RL = 2 kΩ (V−) + 1.6 V
RL = 1 kΩ (V−) + 3.5 V
Voltage Output Swing High RL = 2 kΩ (V+) - 1.6 V
RL = 1 kΩ (V+) − 3.5 V
Short-Circuit Current ISC Sourcing 50 85 mA
Sinking −60 –85
Closed-Loop Output Impedance G = +1, f = 100 kHz 0.22 Ω
Power-Down(1)
Enable Voltage Threshold (V−) + 1.45 V
Disable Voltage Threshold (V−) + 1.4 V
Shutdown Current VS = ±5V, VENABLE = −5 V 0.85 mA
VENABLE = −15 V 1.7 mA
Turn-On Delay Time for IQ to Reach 50% 2 μs
Turn-Off Delay 2 μs
Power Supply
Quiescent Current IQ 13 17.1 mA
Amplifier has internal 250-kΩ pull-up resistor to V+ pin. This enables the amplifier with no connection to shutdown pin.