JAJSD62C March   2013  – January 2020 OPA188


  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      自動ゼロ化技術による、非常に低い温度ドリフト係数の実現
  4. 改訂履歴
  5. Device Comparison Table
    1. 5.1 Portfolio Comparison
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: High-Voltage Operation
    6. 7.6 Electrical Characteristics: Low-Voltage Operation
    7. 7.7 Typical Characteristics: Table of Graphs
      1. 7.7.1 Table of Graphs
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Characteristics
      2. 8.3.2 Phase-Reversal Protection
      3. 8.3.3 Input Bias Current Clock Feedthrough
      4. 8.3.4 Internal Offset Correction
      5. 8.3.5 EMI Rejection
      6. 8.3.6 Capacitive Load and Stability
      7. 8.3.7 Electrical Overstress
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 High-Side Voltage-to-Current (V-I) Converter
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 9.2.2 Discrete INA + Attenuation for ADC With 3.3-V Supply
      3. 9.2.3 Bridge Amplifier
      4. 9.2.4 Low-Side Current Monitor
      5. 9.2.5 Programmable Power Supply
      6. 9.2.6 RTD Amplifier With Linearization
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. TINA-TI(無償のダウンロード・ソフトウェア)
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報



Electrical Overstress

Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress. These questions tend to focus on the device inputs, but may involve the supply voltage pins or the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly.

Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful. See Figure 43 for an illustration of the ESD circuits contained in the OPA188 (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where the diodes meet at an internal absorption device of the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.

An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-current pulse while discharging through a semiconductor device. The ESD protection circuits are designed to provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the protection circuitry is dissipated as heat.

When an ESD voltage develops across two or more amplifier device pins, current flows through one or more steering diodes. Depending on the path that the current takes, the absorption device may activate. The absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPA188 but below the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates and clamps the voltage across the supply rails to a safe level.

When the operational amplifier connects into a circuit (such as Figure 43 shows), the ESD protection components are intended to remain inactive and do not become involved in the operation of the application circuit. However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there is a risk that some internal ESD protection circuits may be biased on and conduct current. Any such current flow occurs through steering-diode paths and rarely involves the absorption device.

Figure 43 shows a specific example where the input voltage, VIN, exceeds the positive supply voltage (+VS) by 500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the current, one of the upper-input steering diodes conducts and directs current to +VS. Excessively high current levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that applications limit the input current to 10 mA.

If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier, and then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to levels that exceed the absolute maximum ratings of the operational amplifier.

Another common question involves what happens to the amplifier if an input signal is applied to the input while the power supplies (+VS or –VS) are at 0 V. Again, this question depends on the supply characteristic while at 0 V, or at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational amplifier supply current may be supplied by the input source through the current-steering diodes. This state is not a normal bias condition; the amplifier will not operate normally. If the supplies are low impedance, then the current through the steering diodes can become quite high. The current level depends on the ability of the input source to deliver current, and any resistance in the input path.

If there is any uncertainty about the ability of the supply to absorb this current, external zener diodes may be added to the supply pins, as shown in Figure 43. The zener voltage must be selected such that the diode does not turn on during normal operation. However, the zener voltage must be low enough so that the zener diode conducts if the supply pin begins to rise above the safe operating supply voltage level.

OPA188 equ_int_esd_circuitry_sbos642.gif
VIN = +VS + 500 mV.
TVS: +VS(max) > VTVSBR(min) > +VS.
Suggested value is approximately 1 kΩ.
Figure 43. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application

The OPA188 input terminals are protected from excessive differential voltage with back-to-back diodes, as shown in Figure 43. In most circuit applications, the input protection circuitry has no consequence. However, in low-gain and G = 1 circuits, fast-ramping input signals can forward-bias these diodes because the output of the amplifier cannot respond rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias condition, the input signal current must be limited to 10 mA or less. If the input signal current is not inherently limited, an input series resistor can be used to limit the signal input current. This input series resistor degrades the low-noise performance of the OPA188 . Figure 43 shows an example configuration that implements a current-limiting feedback resistor.