JAJSFG2I December   2013  – May 2018 OPA172 , OPA2172 , OPA4172

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      JFET入力の低ノイズ・アンプ
      2.      優れたTHD性能
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison
    1. 6.1 Device Comparison
    2. 6.2 Device Family Comparison
  7. 7 Pin Configuration and Functions
    1.     Pin Functions: OPA172
    2.     Pin Functions: OPA2172 and OPA4172
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information: OPA172
    5. 8.5 Thermal Information: OPA2172
    6. 8.6 Thermal Information: OPA4172
    7. 8.7 Electrical Characteristics
    8. 8.8 Typical Characteristics: Table of Graphs
    9. 8.9 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 EMI Rejection
      2. 9.3.2 Phase-Reversal Protection
      3. 9.3.3 Capacitive Load and Stability
    4. 9.4 Device Functional Modes
      1. 9.4.1 Common-Mode Voltage Range
      2. 9.4.2 Electrical Overstress
      3. 9.4.3 Overload Recovery
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Capacitive Load Drive Solution Using an Isolation Resistor
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Bidirectional Current Source
      3. 10.2.3 JFET-Input Low-Noise Amplifier
  11. 11Power-Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
        1. 13.1.1.1 TINA-TI(無料のダウンロード・ソフトウェア)
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Pin Configuration and Functions

DCK Package: OPA172
SC70-5
Top View
OPA172 OPA2172 OPA4172 po_sc70_bos406.gif
DBV Package: OPA172
SOT-23-5
Top View
OPA172 OPA2172 OPA4172 po_sot23-5_bos516.gif
D Package: OPA172
SOIC-8
Top View
OPA172 OPA2172 OPA4172 po_so-8_bos516.gif
1. No internal connection.

Pin Functions: OPA172

PIN I/O DESCRIPTION
NAME OPA172
D (SOIC) DBV (SOT) DCK (SC70)
+IN 3 3 1 I Noninverting input
–IN 2 4 3 I Inverting input
NC 1, 5, 8 — — — No internal connection
OUT 6 1 4 O Output
V+ 7 5 5 — Positive (highest) power supply
V– 4 2 2 — Negative (lowest) power supply
D and DGK Packages: OPA2172
SOIC-8 and VSSOP-8
Top View
OPA172 OPA2172 OPA4172 po_vssop-8_bos516.gif
DRG Package: OPA2172
WSON-8
Top View
OPA172 OPA2172 OPA4172 po_drg_opa1688_sbos724.gif
D and PW Packages: OPA4172
SO-14 and TSSOP-14
Top View
OPA172 OPA2172 OPA4172 po_so-14_bos516.gif

Pin Functions: OPA2172 and OPA4172

PIN I/O DESCRIPTION
NAME OPA2172 OPA4172
D (SOIC),
DGK (VSSOP)		 DRG (WSON) D (SOIC),
PW (TSSOP)
+IN A 3 1 3 I Noninverting input, channel A
+IN B 5 4 5 I Noninverting input, channel B
+IN C — — 10 I Noninverting input, channel C
+IN D — — 12 I Noninverting input, channel D
–IN A 2 8 2 I Inverting input, channel A
–IN B 6 5 6 I Inverting input, channel B
–IN C — — 9 I Inverting input,,channel C
–IN D — — 13 I Inverting input, channel D
OUT A 1 7 1 O Output, channel A
OUT B 7 6 7 O Output, channel B
OUT C — — 8 O Output, channel C
OUT D — — 14 O Output, channel D
V+ 8 2 4 — Positive (highest) power supply
V– 4 3 11 — Negative (lowest) power supply