SBOS688A April   2015  – October 2015 OPA2625 , OPA625


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics High-Drive Mode
    6. 6.6  Electrical Characteristics Low-Power Mode
    7. 6.7  Electrical Characteristics High-Drive Mode
    8. 6.8  Electrical Characteristics Low-Power Mode
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 DC Parameter Measurements
    2. 7.2 Transient Parameter Measurements
    3. 7.3 AC Parameter Measurements
    4. 7.4 Noise Parameter Measurements
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 SAR ADC Driver
      2. 8.3.2 Electrical Overstress
    4. 8.4 Device Functional Modes
      1. 8.4.1 High-Drive Mode
      2. 8.4.2 Low-Power Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Single-Supply, 16-Bit, 1-MSPS SAR ADC Driver
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 9.2.2 Single-Supply, 16-Bit, 1-MSPS, Multiplexed, SAR ADC Driver
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. TINA-TI (Free Software Download)
        2. TI Precision Designs
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information



11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

  • Use bypass capacitors to reduce the noise coupled from the power supply. Connect low ESR, ceramic, bypass capacitors between the power supply pins (V+ and V–) and the ground plane. Place the bypass capacitors as close to the device as possible with the 100-nF capacitor closest to the device, as indicated in Figure 80. For single-supply applications, bypass capacitors on the V– pin are not required.
  • Separate grounding for analog and digital portions of the circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. For more detailed information refer to SLOA089, Circuit Board Layout Techniques.
  • In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.
  • Minimize parasitic coupling between +IN and OUT for best ac performance.
  • Place the external components as close to the device as possible. As shown in Figure 80, keeping RF, CF, and RG close to the inverting input will minimize parasitic capacitance.
  • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
  • Cleaning the PCB following board assembly is recommended for best performance.
  • Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

11.2 Layout Example

OPA625 OPA2625 PCB_1_sbos688.gif Figure 80. PCB Layout Example