JAJSOP2 December   2022 OPT3005

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Human Eye Matching
      2. 8.3.2 Automatic Full-Scale Range Setting
      3. 8.3.3 Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms
      4. 8.3.4 I2C Bus Overview
        1. 8.3.4.1 Serial Bus Address
        2. 8.3.4.2 Serial Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Automatic Full-Scale Setting Mode
      2. 8.4.2 Interrupt Reporting Mechanism Modes
        1. 8.4.2.1 Latched Window-Style Comparison Mode
        2. 8.4.2.2 Transparent Hysteresis-Style Comparison Mode
        3. 8.4.2.3 End-of-Conversion Mode
        4. 8.4.2.4 End-of-Conversion and Transparent Hysteresis-Style Comparison Mode
    5. 8.5 Programming
      1. 8.5.1 Writing and Reading
        1. 8.5.1.1 High-Speed I2C Mode
        2. 8.5.1.2 General-Call Reset Command
        3. 8.5.1.3 SMBus Alert Response
    6. 8.6 Register Maps
      1. 8.6.1 Internal Registers
        1. 8.6.1.1 Register Descriptions
          1. 8.6.1.1.1 Result Register (offset = 00h)
          2. 8.6.1.1.2 Configuration Register (offset = 01h) [reset = C810h]
          3. 8.6.1.1.3 Low-Limit Register (offset = 02h) [reset = C0000h]
          4. 8.6.1.1.4 High-Limit Register (offset = 03h) [reset = BFFFh]
          5. 8.6.1.1.5 Manufacturer ID Register (offset = 7Eh) [reset = 5449h]
          6. 8.6.1.1.6 Device ID Register (offset = 7Fh) [reset = 3001h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Electrical Interface
      2. 9.1.2 Optical Interface
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Optomechanical Design
        2. 9.2.2.2 Dark Window Selection and Compensation
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Power-Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
      3. 9.5.3 Soldering and Handling Recommendations
      4. 9.5.4 Mechanical Drawings
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

All specifications at TA = 25°C, VDD = 3.3 V, 800-ms conversion-time (CT=1)(1), automatic full-scale range (RN[3:0] = 1100b)(1), white LED and normal-angle incidence of light, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Optical
Peak irradiance spectral responsivity 550 nm
Resolution (LSB) Lowest full-scale range, RN[3:0]=0000b(1) 0.02 lux
Full-scale illuminance 167731.2 lux
Measurement Output result 1.28 lux per ADC code, 2620.8 lux full-scale (RN[3:0] = 0101)(1) , 2000 lux input(2) 1250 1563 1875 codes
1600 2000 2400 lux(7)
Relative accuracy between gain ranges (3) 0.2 %
Infrared response (850nm)(2) From -85° to +85° angle of incidence 0.004 %
Linearity Input illuminance > 80 lux 2 %
Input illuminance < 80 lux 5 %
Measurement drift across temperature Input illuminance = 2000 lux 0.06 %/°C
Dark Condition ADC output 0.02 lux per ADC Code 0 3 ADC codes
Half-power-angle 50% of full-power reading 57 degrees
PSRR Power-supply rejection ratio(4) VDD at 3.6 V and 1.6 V 0.1 %/V(3)
POWER SUPPLY
VDD Operating Range 1.6 3.6 V
VI2C Operating range for I2C pull up resistor I2C pullup resistor, VDD ≤ VI2C 1.6 5.5 V
IQ Quiescent current Dark Active, Vdd=3.6V 1.8 2.5 µA
Shutdown (M[1:0]=00)(1), VDD=3.6V 0.3 0.47 µA
Full-scale lux Active, Vdd=3.6V 3.7
Shutdown (M[1:0]=00)(1) 0.4
POR Power-on-reset threshold 0.8 V
DIGITAL
CIO I/O Pin Capacitance 3 pF
Total Integration-time(5) (CT = 1)(1) , 800-ms mode, fixed lux range 720 800 880 ms
(CT = 0)(1) , 100-ms mode, fixed lux range 90 100 110 ms
VIL Low-level input voltage (SDA, SCL, and ADDR) 0 0.3 X VDD V
VIH High-level input voltage (SDA, SCL, and ADDR) 0.7 X VDD 5.5 V
IIL Low-level input current (SDA, SCL, and ADDR) 0.01 0.25(6) µA
VOL Low-level output voltage (SDA and INT) IOL=3mA 0.32 V
IZH Output logic high, high-Z leakage current (SDA, INT) Measured with VDD at pin 0.01 0.25(6) µA
TEMPERATURE
Specified temperature range –40 85 °C
(1) Refers to a control field within the configuration register
(2) Tested with the white LED calibrated to 2k lux and an 850-nm LED
(3) Characterized by measuring fixed near-full-scale light levels on the higher adjacent full-scale range setting.
(4) PSRR is the percent change of the measured lux output from the current value, divided by the change in power supply voltage, as characterized by results from 3.6-V and 1.6-V power supplies.
(5) The conversion-time, from start of conversion until the data are ready to be read, is the integration-time plus 3 ms.
(6) The specified leakage current is dominated by the production test equipment limitations. Typical values are much smaller
(7) equivalent lux measured with white LED @ around 4000K