JAJSTH4A データシート

JAJSTH4A December 2009 – March 2024 SN65MLVD048

PRODUCTION DATA

5.8 Receiver Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
t_PLH	Propagation delay time, low-to-high-level output		C_L = 15pF, See Figure 6-2	2		6	ns
t_PHL	Propagation delay time, high-to-low-level output			2		6	ns
t_r	Output signal rise time			1		2.3
t_f	Output signal fall time			1		2.3	ns
t_sk(p)	Pulse skew (\|t_PHL – t_PLH\|)	Type 1			35	270	ps
t_sk(p)	Pulse skew (\|t_PHL – t_PLH\|)	Type 2			150	460	ps
t_sk(pp)	Part-to-part skew					800	ps
t_jit(per)	Period jitter, rms (1 standard deviation)⁽²⁾		All channels switching, 125MHz clock input⁽³⁾, See Figure 6-4			6	ps
t_jit(c-c)	Cycle-to-cycle jitter, rms⁽²⁾					13	ps
t_jit(det)	Deterministic jitter⁽²⁾	Type 1	All channels switching, 250Mbps 2¹⁵-1 PRBS input⁽³⁾, See Figure 6-4			800	ps
t_jit(det)	Deterministic jitter⁽²⁾	Type 2				945	ps
t_jit(ran)	Random jitter⁽²⁾	Type 1				9	ps
t_jit(ran)	Random jitter⁽²⁾	Type 2				8	ps
t_PZH	Enable time, high-impedance-to-high-level output		C_L = 15pF, See Figure 6-3			15	ns
t_PZL	Enable time, high-impedance-to-low-level output		C_L = 15pF, See Figure 6-3			15	ns
t_PHZ	Disable time, high-level-to-high-impedance output		C_L = 15pF, See Figure 6-3			10	ns
t_PLZ	Disable time, low-level-to-high-impedance output		C_L = 15pF, See Figure 6-3			10	ns

(1) All typical values are at 25°C and with a 3.3V supply voltage.

(2) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.

(3) t_r = t_f = 0.5ns (10% to 90%)