JAJSCW3A December   2016  – February 2020 SN65MLVD206B

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図、 SN65MLVD206B
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. Table 1.  Absolute Maximum Ratings
    2. Table 2.  ESD Ratings
    3. Table 3.  Recommended Operating Conditions
    4. Table 4.  Thermal Information
    5. Table 5.  Electrical Characteristics
    6. Table 6.  Electrical Characteristics – Driver
    7. Table 7.  Electrical Characteristics – Receiver
    8. Table 8.  Electrical Characteristics – BUS Input and Output
    9. Table 9.  Switching Characteristics – Driver
    10. Table 10. Switching Characteristics – Receiver
    11. 7.1       Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Power-On-Reset
      2. 9.3.2 ESD Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation with VCC < 1.5 V
      2. 9.4.2 Operations with 1.5 V ≤ VCC < 3 V
      3. 9.4.3 Operation with 3 V ≤ VCC < 3.6 V
      4. 9.4.4 Device Function Tables
      5. 9.4.5 Equivalent Input and Output Schematic Diagrams
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Multipoint Communications
      2. 10.2.2 Design Requirements
      3. 10.2.3 Detailed Design Procedure
        1. 10.2.3.1  Supply Voltage
        2. 10.2.3.2  Supply Bypass Capacitance
        3. 10.2.3.3  Driver Input Voltage
        4. 10.2.3.4  Driver Output Voltage
        5. 10.2.3.5  Termination Resistors
        6. 10.2.3.6  Receiver Input Signal
        7. 10.2.3.7  Receiver Input Threshold (Failsafe)
        8. 10.2.3.8  Receiver Output Signal
        9. 10.2.3.9  Interconnecting Media
        10. 10.2.3.10 PCB Transmission Lines
      4. 10.2.4 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Microstrip vs. Stripline Topologies
      2. 12.1.2 Dielectric Type and Board Construction
      3. 12.1.3 Recommended Stack Layout
      4. 12.1.4 Separation Between Traces
      5. 12.1.5 Crosstalk and Ground Bounce Minimization
      6. 12.1.6 Decoupling
        1.       (a)
        2.       (b)
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.2 ESD Protection

The bus terminals of the SN65MLVD206B possess on-chip ESD protection against ±8-kV human body model (HBM) and ±8-kV IEC61000-4-2 contact discharge. The IEC-ESD test is far more severe than the HBM-ESD test. The 50% higher charge capacitance, CS, and 78% lower discharge resistance, RD of the IEC model produce significantly higher discharge currents than the HBM-model.

As stated in the IEC 61000-4-2 standard, contact discharge is the preferred test method; although IEC air-gap testing is less repeatable than contact testing, air discharge protection levels are inferred from the contact discharge test results.

SN65MLVD206B hbm_app_sllsen0.gifFigure 15. HBM and IEC-ESD Models and Currents in Comparison (HBM Values in Parenthesis)