JAJSS65 November   2023 SN74LV4T00-EP

PRODUCTION DATA  

1.   1
2. 1 特長
3. 2 アプリケーション
4. 3 概要
5. 4 Pin Configuration and Functions
6. 5 Specifications
   1. 5.1 Absolute Maximum Ratings
   2. 5.2 ESD Ratings
   3. 5.3 Recommended Operating Conditions
   4. 5.4 Thermal Information
   5. 5.5 Electrical Characteristics
   6. 5.6 Switching Characteristics
   7. 5.7 Noise Characteristics
   8. 5.8 Typical Characteristics
7. 6 Parameter Measurement Information
8. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagram
   3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS 3-State Outputs
      2. 7.3.2 Clamp Diode Structure
      3. 7.3.3 LVxT Enhanced Input Voltage
         1. 7.3.3.1 Down Translation
         2. 7.3.3.2 Up Translation
   4. 7.4 Device Functional Modes
9. 8 Application and Implementation
   1. 8.1 Application Information
   2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
         1. 8.2.1.1 Power Considerations
         2. 8.2.1.2 Input Considerations
         3. 8.2.1.3 Output Considerations
      2. 8.2.2 Application Curves
10. 9 Power Supply Recommendations
11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
12. 11Device and Documentation Support
    1. 11.1 Documentation Support
       1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
13. 12Revision History
14. 13Mechanical, Packaging, and Orderable Information