JAJSD19B データシート

JAJSD19B August 2015 – February 2019 TAS2555

PRODUCTION DATA.

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

YZ|42

サーマルパッド・メカニカル・データ

発注情報

8.5 Electrical Characteristics

V_BAT = 3.6V, AVDD = DVDD = IOVDD = 1.8 V, RESET = IOVDD, Gain = 16.4 dB, ERC = 14ns, Boost Inductor = 2.2 µH, R_L = 8 Ω + 33 µH, 1-kHz input frequency, 48- kHz sample rate for digital input, Class-H Boost Enabled, T_A= 25°C, ILIM = 3 A (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
BOOST CONVERTER
	Boost Output Voltage	Average voltage (w/o including ripple).		8.5		V
	Boost Converter Switching Frequency			1.77		MHz
	Boost Converter Current Limit			3		A
	Boost Converter Max In-Rush Current	High Efficiency Mode: Max inductor inrush and startup current after enable		4		A
	Boost Converter Max In-Rush Current	Normal Efficiency Mode: Max inductor inrush and startup current after enable		1.5		A
CLASS-D CHANNEL
	Output Voltage for Full-Scale Digital Input			6.6		V_RMS
	Load Resistance (Load Spec Resistance)		3.6	8		Ω
	Class-D Frequency	Avg Frequency in Spread-Spectrum Mode		384		kHz
	Class-D Frequency	Fixed Frequency	44.1 × 8	48 × 8		kHz
	Class-D + Boost Efficiency	P_OUT = 3.5 W (sinewave) ROM Mode 1		80		%
	Class-D + Boost Efficiency	P_OUT = 0.5 W (sinewave) ROM Mode 1		87		%
	Class-D Output Current Limit (Short Circuit Protection)	VBOOST = 8.5 V, OUT– shorted to VBAT, VBOOST, GND		6		A
	Class-D Output Offset Voltage in Digital Input Mode		–2.5		2.5	mV
	Programmable Channel Gain Accuracy			±0.5		dB
	Mute Attenuation	Device in shutdown or device in normal operation and MUTED		150		dB
	VBAT Power Supply Rejection Ratio (PSRR)	Ripple of 200 mVpp at 217 Hz		110		dB
	AVDD Power Supply Rejection Ratio (PSRR)	Ripple of 200 mVpp at 217 Hz		99		dB
	THD+N	1 kHz, P_OUT = 0.1 W		0.0041		%
		1 kHz, Po = 0.5 W		0.0036
		1 kHz, Po = 1 W		0.0035
		1 kHz, Po = 3 W		0.02
	Output Integrated Noise (20 Hz-20 kHz) - 8 Ω	A-wt Filter, DAC modulator switching		15.9		µV
	Signal-to-noise ratio	Referenced to 1% THD+N at output, a-weighted		110.6		dB
	Max Output Power, 3-A Current Limit	THD+N=1%, 8-Ω Load		3.7		W
		THD+N=1%, 6-Ω Load		4.5
		THD+N=1%, 4-Ω Load		5
	Startup Pop	Digital Input, A-weighted output		10		mV
	Output Impedance in Shutdown	/RESET = 0 V		10		kΩ
	Startup Time	Time taken from end of configuring device in ROM mode1/2 to Speaker output signal in SPI mode running at 25 MHz with 48 ksps input		8		mS
	Shutdown Time	Measured from time when device is programmed in software shutdown mode		100		µS
CURRENT SENSE
	Current Sense Full Scale	Peak current which will give full scale digital output 8-Ω load		1.25		A_PEAK
		Peak current which will give full scale digital output 6-Ω load		1.48
		Peak current which will give full scale digital output 4-Ω load		1.76
	Current Sense Accuracy	I_OUT = 354 mA_RMS (1 W)		1		%
VOLTAGE SENSE
	Voltage Sense Full Scale	Peak voltage which will give full scale digital output		8.5		V_PEAK
	Voltage Sense Accuracy	V_OUT = 2.83 Vrms (1 W)		1		%
INTERFACE
	Voltage and Current Sense Data Rate	TDM/I2S		48		kHz
	Voltage and Current Sense ADC OSR	TDM/I2S		64		OSR
F_MCLK	MCLK frequency		0.512		49.15	MHz
POWER CONSUMPTION
	Power Consumption with Digital Input and Speaker Protection Disabled (ROM MODE 1)	From VBAT, PLL off, no signal		3		mA
		From AVDD, PLL off, no signal		1.7		mA
		From DVDD, PLL off, no signal		3.9		mA
	Power Consumption with Digital Input and Speaker Protection Enabled	From VBAT, PLL on, no signal		3		mA
		From AVDD, PLL on, no signal		3.4		mA
		From DVDD, PLL on, no signal		20		mA
	Power Consumption in Hardware Shutdown	From VBAT, /RESET = 0		0.1		µA
		From AVDD, /RESET = 0		0.2		µA
		From DVDD, /RESET = 0		1		µA
	Power Consumption in Software Shutdown See Low Power Sleep Mode	From VBAT		0.1		µA
		From AVDD		0.1		µA
		From DVDD		9.7		µA
DIGITAL INPUT / OUTPUT
V_IH	High-level digital input voltage	All digital pins except SDA and SCL, IOVDD = 1.8-V operation	0.65 × IOVDD			V
V_IL	Low-level digital input voltage				0.35 × IOVDD	V
V_IH	High-level digital input voltage	All digital pins except SDA and SCL, IOVDD = 3.3-V operation	2			V
V_IL	Low-level digital input voltage				0.45	V
V_OH	High-level digital output voltage	All digital pins except SDA and SCL, IOVDD = 1.8-V operation For I_OL = 2 mA and I_OH = –2 mA	IOVDD – 0.45			V
V_OL	Low-level digital output voltage				0.45	V
V_OH	High-level digital output voltage	All digital pins except SDA and SCL, IOVDD = 3.3-V operation For I_OL = 2 mA and I_OH = –2 mA	2.4			V
V_OL	Low-level digital output voltage				0.4	V
I_IH	High-level digital input leakage current	Input = IOVDD	–5	0.1	5	µA
I_IL	Low-level digital input leakage current	Input = Ground	–5	0.1	5	µA
MISCELLANEOUS
T_TRIP	Thermal Trip Point			140		°C