JAJSGV7D April   2019  – January 2024 TAS2563

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  I2C Timing Requirements
    7. 5.7  SPI Timing Requirements
    8. 5.8  PDM Port Timing Requirements
    9. 5.9  TDM Port Timing Requirements
    10. 5.10 Timing Diagrams
    11. 5.11 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PurePath Console 3 Software
      2. 7.3.2  Device Mode and Address Selection
      3. 7.3.3  General I2C Operation
      4. 7.3.4  General SPI Operation
      5. 7.3.5  Single-Byte and Multiple-Byte Transfers
      6. 7.3.6  Single-Byte Write
      7. 7.3.7  Multiple-Byte Write and Incremental Multiple-Byte Write
      8. 7.3.8  Single-Byte Read
      9. 7.3.9  Multiple-Byte Read
      10. 7.3.10 Register Organization
      11. 7.3.11 Operational Modes
        1. 7.3.11.1 Hardware Shutdown
        2. 7.3.11.2 Software Shutdown
        3. 7.3.11.3 Mute
        4. 7.3.11.4 Active
        5. 7.3.11.5 Perform Load Diagnostics
        6. 7.3.11.6 Mode Control and Software Reset
      12. 7.3.12 Faults and Status
      13. 7.3.13 Digital Input Pull Downs
    4. 7.4 Device Functional Modes
      1. 7.4.1 PDM Input
      2. 7.4.2 TDM Port
      3. 7.4.3 Playback Signal Path
        1. 7.4.3.1 Digital Signal Processor
        2. 7.4.3.2 High Pass Filter
        3. 7.4.3.3 Digital Volume Control and Amplifier Output Level
        4. 7.4.3.4 Auto-mute During Idle Channel Mode
        5. 7.4.3.5 Auto-start/stop on Audio Clocks
        6. 7.4.3.6 Supply Tracking Limiters with Brown Out Prevention
        7. 7.4.3.7 Class-D Settings
      4. 7.4.4 SAR ADC
      5. 7.4.5 Boost
      6. 7.4.6 IV Sense
      7. 7.4.7 Load Diagnostics
      8. 7.4.8 Clocks and PLL
      9. 7.4.9 Thermal Foldback
    5. 7.5 Register Maps
      1. 7.5.1  Register Summary Table Page=0x00
      2. 7.5.2  PAGE (page=0x00 address=0x00) [reset=0h]
      3. 7.5.3  SW_RESET (page=0x00 address=0x01) [reset=0h]
      4. 7.5.4  PWR_CTL (page=0x00 address=0x02) [reset=Eh]
      5. 7.5.5  PB_CFG1 (page=0x00 address=0x03) [reset=20h]
      6. 7.5.6  MISC_CFG1 (page=0x00 address=0x04) [reset=C6h]
      7. 7.5.7  MISC_CFG2 (page=0x00 address=0x05) [reset=22h]
      8. 7.5.8  TDM_CFG0 (page=0x00 address=0x06) [reset=9h]
      9. 7.5.9  TDM_CFG1 (page=0x00 address=0x07) [reset=2h]
      10. 7.5.10 TDM_CFG2 (page=0x00 address=0x08) [reset=4Ah]
      11. 7.5.11 TDM_CFG3 (page=0x00 address=0x09) [reset=10h]
      12. 7.5.12 TDM_CFG4 (page=0x00 address=0x0A) [reset=13h]
      13. 7.5.13 TDM_CFG5 (page=0x00 address=0x0B) [reset=2h]
      14. 7.5.14 TDM_CFG6 (page=0x00 address=0x0C) [reset=0h]
      15. 7.5.15 TDM_CFG7 (page=0x00 address=0x0D) [reset=4h]
      16. 7.5.16 TDM_CFG8 (page=0x00 address=0x0E) [reset=5h]
      17. 7.5.17 TDM_CFG9 (page=0x00 address=0x0F) [reset=6h]
      18. 7.5.18 TDM_CFG10 (page=0x00 address=0x10) [reset=7h]
      19. 7.5.19 DSP Mode & TDM_DET (page=0x00 address=0x11) [reset=7Fh]
      20. 7.5.20 LIM_CFG0 (page=0x00 address=0x12) [reset=12h]
      21. 7.5.21 LIM_CFG1 (page=0x00 address=0x13) [reset=76h]
      22. 7.5.22 DSP FREQUENCY & BOP_CFG0 (page=0x00 address=0x14) [reset=1h]
      23. 7.5.23 BOP_CFG0 (page=0x00 address=0x15) [reset=2Eh]
      24. 7.5.24 BIL_and_ICLA_CFG0 (page=0x00 address=0x16) [reset=60h]
      25. 7.5.25 BIL_ICLA_CFG1 (page=0x00 address=0x17) [reset=0h]
      26. 7.5.26 GAIN_ICLA_CFG0 (page=0x00 address=0x18) [reset=0h]
      27. 7.5.27 ICLA_CFG1 (page=0x00 address=0x19) [reset=0h]
      28. 7.5.28 INT_MASK0 (page=0x00 address=0x1A) [reset=FCh]
      29. 7.5.29 INT_MASK1 (page=0x00 address=0x1B) [reset=A6h]
      30. 7.5.30 INT_MASK2 (page=0x00 address=0x1C) [reset=DFh]
      31. 7.5.31 INT_MASK3 (page=0x00 address=0x1D) [reset=FFh]
      32. 7.5.32 INT_LIVE0 (page=0x00 address=0x1F) [reset=0h]
      33. 7.5.33 INT_LIVE1 (page=0x00 address=0x20) [reset=0h]
      34. 7.5.34 INT_LIVE3 (page=0x00 address=0x21) [reset=0h]
      35. 7.5.35 INT_LIVE4 (page=0x00 address=0x22) [reset=0h]
      36. 7.5.36 INT_LTCH0 (page=0x00 address=0x24) [reset=0h]
      37. 7.5.37 INT_LTCH1 (page=0x00 address=0x25) [reset=0h]
      38. 7.5.38 INT_LTCH3 (page=0x00 address=0x26) [reset=0h]
      39. 7.5.39 INT_LTCH4 (page=0x00 address=0x27) [reset=0h]
      40. 7.5.40 VBAT_MSB (page=0x00 address=0x2A) [reset=0h]
      41. 7.5.41 VBAT_LSB (page=0x00 address=0x2B) [reset=0h]
      42. 7.5.42 TEMP (page=0x00 address=0x2C) [reset=0h]
      43. 7.5.43 INT & CLK CFG (page=0x00 address=0x30) [reset=19h]
      44. 7.5.44 DIN_PD (page=0x00 address=0x31) [reset=40h]
      45. 7.5.45 MISC (page=0x00 address=0x32) [reset=80h]
      46. 7.5.46 BOOST_CFG1 (page=0x00 address=0x33) [reset=34h]
      47. 7.5.47 BOOST_CFG2 (page=0x00 address=0x34) [reset=4Bh]
      48. 7.5.48 BOOST_CFG3 (page=0x00 address=0x35) [reset=74h]
      49. 7.5.49 MISC (page=0x00 address=0x3B) [reset=58h]
      50. 7.5.50 TG_CFG0 (page=0x00 address=0x3F) [reset=0h]
      51. 7.5.51 BST_ILIM_CFG0 (page=0x00 address=0x40) [reset=36h]
      52. 7.5.52 PDM_CONFIG0 (page=0x00 address=0x41) [reset=1h]
      53. 7.5.53 DIN_PD & PDM_CONFIG3 (page=0x00 address=0x42) [reset=F8h]
      54. 7.5.54 ASI2_CONFIG0 (page=0x00 address=0x43) [reset=8h]
      55. 7.5.55 ASI2_CONFIG1 (page=0x00 address=0x44) [reset=0h]
      56. 7.5.56 ASI2_CONFIG2 (page=0x00 address=0x45) [reset=1h]
      57. 7.5.57 ASI2_CONFIG3 (page=0x00 address=0x46) [reset=FCh]
      58. 7.5.58 PVDD_MSB_DSP (page=0x00 address=0x49) [reset=0h]
      59. 7.5.59 PVDD_LSB_DSP (page=0x00 address=0x4A) [reset=0h]
      60. 7.5.60 REV_ID (page=0x00 address=0x7D) [reset=0h]
      61. 7.5.61 I2C_CKSUM (page=0x00 address=0x7E) [reset=0h]
      62. 7.5.62 BOOK (page=0x00 address=0x7F) [reset=0h]
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 Boost Converter Passive Devices
        3. 8.2.2.3 EMI Passive Devices
        4. 8.2.2.4 Miscellaneous Passive Devices
      3. 8.2.3 Application Curves
  10. Power Supply Recommendations
    1. 9.1 Power Supplies
    2. 9.2 Power Supply Sequencing
      1. 9.2.1 Boost Supply Details
      2. 9.2.2 External Boost Mode (Boost Bypass Mode)
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • YBG|42
  • RPP|32
サーマルパッド・メカニカル・データ
発注情報

Supply Tracking Limiters with Brown Out Prevention

The TAS2563 monitors battery voltage (VBAT) and the class-D voltage (PVDD) along with the audio signal to automatically decrease gain when the audio signal peaks exceed a programmable threshold. This helps prevent clipping and extends playback time through end of charge battery conditions. The limiters threshold can be configured to track the monitored voltage below a programmable inflection point with a programmable slope. A minimum threshold sets the limit of threshold reduction from the voltage tracking. Configurable attack rate, hold time and release rate are provided to shape the dynamic response of each limiter. The total attenuation is the sum of both the VBAT and PVDD limiter. If the ICLA is enabled the actual attenuation is based on the ICLA configuration using the calculated attenuation value of all devices on the selected ICLA bus.

A Brown Out Prevention (BOP) feature provides a priority input to provide a very fast response to transient dips in the battery supply (VBAT) which at end of charge conditions that can cause system level brown out. When the selected supply dips below the brown-out threshold the BOP will begin reducing gain with an first attack latency of less than 10 µs and a configurable attack rate. When the VBAT supply rises above the brownout threshold, the BOP will begin to release after the programmed hold time. During a BOP event the limiter updates will be paused. This is to prevent a limiter from releasing during a BOP event. The VBAT and PVDD limiters are enabled by setting the respective LIMB_EN and LIMP_EN bits high.

Table 7-58 VBAT Tracking Limiter Enable
LIMB_ENVALUE
0
Disabled (default)
1
Enabled
Table 7-59 PVDD Tracking Limiter Enable
LIMP_ENVALUE
0
Disabled (default)
1
Enabled

The limiters have configurable attack rates, hold times and release rates, which are available via the LIMB_ATK_RT[2:0], LIMB_HLD_TM[2:0], LIMB_RLS_RT[2:0] register bits respectively for VBAT and LIMP_ATK_RT[2:0], LIMP_HLD_TM[2:0], LIMP_RLS_RT[2:0] register bits respectively for PVDD . The limiters attack and release step sizes can be set by configuring the LIMB_ATK_ST[1:0] and LIMB_RLS_ST[1:0] register bits respectively for VBAT and LIMP_ATK_ST[1:0] and LIMP_RLS_ST[1:0] register bits respectively for PVDD. For sampling rates less that 44.1kHz and greater than 8 kHz the minimum attack rate is 20µs and for sampling rates of 8kHz or less the minimum attack rate is 40µs.

A maximum level of attenuation applied by the limiters and brown out prevention feature is configurable via the LIM_MAX_ATN register. This attenuation limit is shared between the features. For instance, if the maximum attenuation is set to 6 dB and the limiters have reduced gain by 4 dB, the brown out prevention feature will only be able to reduce the gain further by another 2 dB. If the limiter or brown out prevention feature is attacking and it reaches the maximum attenuation, gain will not be reduced any further.

The limiter max attenuation LIM_MAX_ATN represent the limit in a 1.X format. To calculate the value to write to the 4 registers by apply the following formula to the desired dB using equation LIMB_MAX_ATN = round(10^(-dB/20)*2^31).

Table 7-60 Limiter Max Attenuation
LIM_MAX_ATN[31:0]ATTENUATION (dB)
0x7214 82C0
-1
...
...
0x2D6A 866F
-9 (default)
...
...
0x1326 DD71
-16.5

The limiter begins reducing gain when the output signal level is greater than the limiter threshold. The limiter can be configured to track selected supply below a programmable inflection point with a minimum threshold value. Figure 7-15 below shows the limiter configured to limit to a constant level regardless of the selected supply level. To achieve this behavior, set the limiter maximum threshold to the desired level using LIM_TH_MAX. Set the limiter inflection point using LIM_INF_PT below the minimum allowable supply setting. The limiter minimum threshold register LIM_TH_MIN does not impact limiter behavior in this use case.

GUID-E127E6BC-272E-4BC3-B95C-78E5267AC896-low.gifFigure 7-15 Limiter with Fixed Threshold

The VBAT limiter threshold max LIMB_TH_MAX and min LIMB_TH_MIN registers represent the limit in a 5.X format. To calculate the value to write to the 4 registers by apply the following formula to the desired threshold voltage using the equation LIMB_TH_MAX or LIMB_TH_MIN = round(Volts*2^27).

Table 7-61 VBAT Limiter Maximum Threshold
LIMB_TH_MAX[31:0]THRESHOLD (V)
0x1400 0000
2.5
...
...
0x4800 0000
9 (default)
...
...
0x7C00 0000
15.5
Table 7-62 VBAT Limiter Minimum Threshold
LIMB_TH_MIN[31:0]THRESHOLD (V)
0x1400 0000
2.5
...
...
0x2000 0000
4 (default)
...
...
0x7C00 0000
15.5

The VBAT limiter inflection point LIMB_INF_PT represent the limit in a 5.X format. To calculate the value to write to the 4 registers by apply the following formula to the desired infection voltage using the equation LIMB_INF_PT = round(Volts*2^27).

Table 7-63 VBAT Limiter Inflection Point
LIMB_INF_PT[31:0]THRESHOLD (V)
0x2000 0000
2
...
...
0x34CC CCCD
3.3 (default)
...
...
0x3000 0000
6

Figure 7-16 shows how to configure the limiter to track selected supply below a threshold without a minimum threshold. Set the LIM_TH_MAX register to the desired threshold and LIM_INF_PT register to the desired inflection point where the limiter will begin reducing the threshold with the selected supply. The default value of 1 V/V will reduce the threshold 1 V for every 1 V of drop in the supply voltage. More aggressive tracking slopes can be programmed if desired. Program the LIM_TH_MIN below the minimum the selected supply to prevent the limiter from having a minimum threshold reduction when tracking the selected supply.

The VBAT limiter tracking slope LIMB_SLOPE[31:0] represent the limit in a 5.X format. To calculate the value to write to the 4 registers by apply the following formula to the desired infection voltage using equation LIMB_SLOPE = round(slope(V/V)*2^27)

GUID-C3DA6C1D-915D-42B5-8BC6-6E2836F91E8C-low.gifFigure 7-16 Limiter with Inflection Point

To achieve a limiter that tracks the selected supply below a threshold, configure the limiter as explained in the previous example, except program the LIM_TH_MIN register to the desired minimum threshold. This is shown in Figure 7-17 below.

GUID-48891091-3031-4E3E-BFC2-55A734FF8689-low.gifFigure 7-17 Limiter with Inflection Point and Minimum Threshold

The TAS2563 also employs a Brown Out Prevention (BOP) feature that serves as a low latency priority input to the limiter engine that begins attacking the VBAT supply dipping below the programmed BOP threshold. This feature can be enabled by setting the BOP_EN register bit high. It should be noted that the BOP feature is independent of the limiter and will function if enabled, even if the limiter is disabled. The BOP threshold is configured by setting the threshold with register bits BOP_TH.

Table 7-64 Brown Out Prevention Enable
BOP_ENVALUE
0
Disabled
1
Enabled (default)

The Brownout prevention threshold BOP_TH represent a threshold in a 5.X format. To calculate the value to write to the 4 registers by apply the following formula to the desired brownout threshold using equation BOP_TH = round(Volts*2^27).

Table 7-65 Brown Out Prevention Threshold
BOP_TH[31:0]VBAT THRESHOLD (V)
0x0000 000 - 0x1FFF FFFF
Reserved
0x2000 0000
2.5
...
...
0x2E66 6666
2.9 (default)
...
...
0x2000 0000
4
0x2000 0001 - 0xFFFF FFFF
Reserved

The BOP feature has a separate attack rate BOP_ATK_RT, attack step size BOP_ATK_ST and hold time BOP_HLD_TM from the battery tracking limiter. The BOP feature uses the LIMB_RLS_RT register setting to release after a brown out event. The rates are based on the number of audio samples and actual time values can be calculated by multiplying by 1/fs. For example the attack rate of 4 samples at 48 ksps would be approximately 83 µs.

Table 7-66 Brown Out Prevention Attack Rate
BOP_ATK_RT[2:0]ATTACK RATE (samples/step)ATTACK RATE @ 48 ksps (~µs)
0x0
120
0x1
242
0x2
483
0x3
8167
0x4
16333
0x5
32666
0x6
641300
0x7
1282700
Table 7-67 Brown Out Prevention Attack Step Size
BOP_ATK_ST[1:0]STEP SIZE (dB)
00
0.5
01
1 (default)
10
1.5
11
2
Table 7-68 Brown Out Prevention Hold Time
BOP_HLD_TM[2:0]HOLD TIME (ms)
0x0
0
0x1
10
0x2
25
0x3
50
0x4
100
0x5
250
0x6
500 (default)
0x7
1000

The TAS2563 can also shutdown the device when a brown out event occurs if the BOP_MUTE register bit is set high. For the device to continue playing audio again, the device must transition through a SW/HW shutdown state. Setting the BOP_INF_HLD high will cause the limiter to stay in the hold state (i.e. never release) after a cleared brown out event until either the device transitions through a mute or SW/HW shutdown state or the register bit BOP_HLD_CLR is written to a high value (which will cause the device to exit the hold state and begin releasing). This bit is self clearing and will always readback low. Figure 7-18 below illustrates the entering and exiting from a brown out event.

GUID-5D03A677-846F-4CC2-8D63-CF4688E48612-low.gifFigure 7-18 Brown Out Prevention Event
Table 7-69 Shutdown on Brown Out Event
BOP_MUTEVALUE
0
Don't Shutdown (default)
1
Mute then shutdown
Table 7-70 Infinite Hold on Brown Out Event
BOP_INF_HLDVALUE
0
Use BOP_HLD_TM after Brown Out event (default)
1
Do not release until BOP_HLD_CLR is asserted high
Table 7-71 BOP Infinite Hold Clear
BOP_HLD_CLRVALUE
0
Don't clear (default)
1
Clear event (self clearing)

A hard brownout level can be set to shutdown the TAS2563 if the BOP cannot mitigate the drop in battery voltage VBAT. This will shutdown the device and should not be used if the BOP_MUTE is enable. The brownout shutdown will only function if brownout engine is enabled using BOP_EN.

Table 7-72 Brown Out Shutdown Enable
BOSD_ENVALUE
0
Disabled (default)
1
Enabled

The Brownout prevention shutdown threshold BOSD_TH represent a threshold in a 5.X format. To calculate the value to write to the 4 registers by apply the following formula to the desired brownout threshold using equation BOSD_TH = round(Volts*2^27).

Table 7-73 Brown Out Shutdown Threshold
BOSD_TH[31:0]VBAT THRESHOLD (V)
0x2000 0000
2.5
...
...
0x2B33 3333
2.7 (default)
...
...
0x3FFF FFFF
3.99