JAJSIZ0A April   2020  – July 2020 TAS5431-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements for I2C Interface Signals
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Audio Input and Preamplifier
      2. 7.3.2 Pulse-Width Modulator (PWM)
      3. 7.3.3 Gate Drive
      4. 7.3.4 Power FETs
      5. 7.3.5 Load Diagnostics
        1. 7.3.5.1 Load Diagnostics Sequence
        2. 7.3.5.2 Faults During Load Diagnostics
      6. 7.3.6 Protection and Monitoring
      7. 7.3.7 I2C Serial Communication Bus
        1. 7.3.7.1 I2C Bus Protocol
        2. 7.3.7.2 Random Write
        3. 7.3.7.3 Random Read
        4. 7.3.7.4 Sequential Read
    4. 7.4 Device Functional Modes
      1. 7.4.1 Hardware Control Pins
      2. 7.4.2 EMI Considerations
      3. 7.4.3 Operating Modes and Faults
    5. 7.5 Register Maps
      1. 7.5.1 I2C Address Register Definitions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Amplifier Output Filtering
        2. 8.2.1.2 Amplifier Output Snubbers
        3. 8.2.1.3 Bootstrap Capacitors
        4. 8.2.1.4 Analog Audio Input Filter
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Unused Pin Connections
          1. 8.2.2.1.1 MUTE Pin
          2. 8.2.2.1.2 STANDBY Pin
          3. 8.2.2.1.3 I2C Pins (SDA and SCL)
          4. 8.2.2.1.4 Terminating Unused Outputs
          5. 8.2.2.1.5 Using a Single-Ended Audio Input
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
      1. 10.2.1 Top Layer
      2. 10.2.2 Second Layer – Signal Layer
      3. 10.2.3 Third Layer – Power Layer
      4. 10.2.4 Bottom Layer – Ground Layer
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード パーティ製品に関する免責事項
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
V(PVDD_OP) Supply voltage range relative to GND. Includes ac transients, requires proper decoupling.(3) 4-Ω ±20% load (or higher) 4.5 14.4 18 V
2-Ω ±20% load 5 14.4 18
V(PVDD_RIPPLE) Maximum ripple on PVDD V(PVDD) < 8 V 1 Vpp
V(MUTE) MUTE pin voltage range relative to GND -0.3 3.3 5.5 V
V(AIN) (1) Analog audio input-signal level AC-coupled input voltage 0 0.25–1(2) Vrms
V(IH_STANDBY) MUTE and STANDBY pins input voltage for logic-level high 2 V
V(IL_STANDBY) MUTE and STANDBY pins input voltage for logic-level low 0.7 V
V(IH_SCL) SCL pin input voltage for logic-level high R(PU_I2C) = 4.7-kΩ pullup, supply voltage = 3.3 V or 5 V 2.1 V
V(IH_SDA) SDA pin input voltage for logic-level high R(PU_I2C) = 4.7-kΩ pullup, supply voltage = 3.3 V or 5 V 2.1 V
V(IL_SCL) SCL pin input voltage for logic-level low R(PU_I2C) = 4.7-kΩ pullup, supply voltage = 3.3 V or 5 V 1.1 V
V(IL_SDA) SDA pin input voltage for logic-level low R(PU_I2C) = 4.7-kΩ pullup, supply voltage = 3.3 V or 5 V 1.1 V
TA Ambient temperature –40 125 °C
R(L) Nominal speaker load impedance When using low-impedance loads, do not exceed overcurrent limit. 2 4 16 Ω
V(PU) Pullup voltage supply (for open-drain logic outputs) V(PU) must be less than (V(PVDD) - 1V) during normal operation. 3 3.3 5.5 V
R(PU_EXT) External pullup resistor on open-drain logic outputs Resistor connected between open-drain logic output and V(PU) supply. 10 50 kΩ
R(PU_I2C) I2C pullup resistance on SDA and SCL pins 1 4.7 10 kΩ
C(PVDD) External capacitor on the PVDD pin, typical value ± 20%(3) 10 μF
C(BYP) External capacitor on the BYP pin, typical value ± 10% 1 μF
C(OUT) External capacitance to GND on OUT_X pins 4 μF
C(IN) External capacitance to analog input pin in series with input signal 1 μF
C(BSTN), C(BSTP) External boostrap capacitor, typical value ± 20% 220 nF
(1) Signal input for full unclipped output with gains of 36 dB, 32 dB, 26 dB, and 20 dB
(2) Maximum recommended input voltage is determined by the gain setting.
(3) See the section.