JAJSIZ0A April   2020  – July 2020 TAS5431-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements for I2C Interface Signals
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Audio Input and Preamplifier
      2. 7.3.2 Pulse-Width Modulator (PWM)
      3. 7.3.3 Gate Drive
      4. 7.3.4 Power FETs
      5. 7.3.5 Load Diagnostics
        1. 7.3.5.1 Load Diagnostics Sequence
        2. 7.3.5.2 Faults During Load Diagnostics
      6. 7.3.6 Protection and Monitoring
      7. 7.3.7 I2C Serial Communication Bus
        1. 7.3.7.1 I2C Bus Protocol
        2. 7.3.7.2 Random Write
        3. 7.3.7.3 Random Read
        4. 7.3.7.4 Sequential Read
    4. 7.4 Device Functional Modes
      1. 7.4.1 Hardware Control Pins
      2. 7.4.2 EMI Considerations
      3. 7.4.3 Operating Modes and Faults
    5. 7.5 Register Maps
      1. 7.5.1 I2C Address Register Definitions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Amplifier Output Filtering
        2. 8.2.1.2 Amplifier Output Snubbers
        3. 8.2.1.3 Bootstrap Capacitors
        4. 8.2.1.4 Analog Audio Input Filter
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Unused Pin Connections
          1. 8.2.2.1.1 MUTE Pin
          2. 8.2.2.1.2 STANDBY Pin
          3. 8.2.2.1.3 I2C Pins (SDA and SCL)
          4. 8.2.2.1.4 Terminating Unused Outputs
          5. 8.2.2.1.5 Using a Single-Ended Audio Input
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
      1. 10.2.1 Top Layer
      2. 10.2.2 Second Layer – Signal Layer
      3. 10.2.3 Third Layer – Power Layer
      4. 10.2.4 Bottom Layer – Ground Layer
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード パーティ製品に関する免責事項
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

TC = 25°C, PVDD = 14.4 V, RL = 4 Ω, P(O) = 1 W/ch, AES17 filter, default I2C settings (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING CURRENT
PVDD idle current In PLAY mode, no audio present 16 mA
PVDD standby current STANDBY mode, MUTE = 0 V 5 20 µA
OUTPUT POWER
Output power per channel 4 Ω, THD+N ≤ 1%, 1 kHz, TC = 75°C 6 W
4 Ω, THD+N = 10%, 1 kHz, TC = 75°C 8
Power efficiency 4 Ω, P(O) = 8 W (10% THD) 83%
AUDIO PERFORMANCE
Noise voltage at output G = 20 dB, zero input, and A-weighting 65 µV
Common-mode rejection ratio f = 1 kHz, 100 mVrms referenced to GND, G = 20 dB 63 dB
Power-supply rejection ratio PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz 75
Total harmonic distortion + noise P(O) = 1 W, f = 1 kHz 0.05%
Switching frequency Switching frequency selectable for AM interference avoidance 400 kHz
500
Internal common-mode input bias voltage Internal bias applied to IN_N, IN_P pins 3 V
Voltage gain (VO / VIN) Source impedance = 0 Ω, register 0x03 bits 7–6 = 00 19 20 21 dB
Source impedance = 0 Ω, register 0x03 bits 7–6 = 01 25 26 27
Source impedance = 0 Ω, register 0x03 bits 7–6 = 10 31 32 33
Source impedance = 0 Ω, register 0x03 bits 7–6 = 11 35 36 37
PWM OUTPUT STAGE
FET drain-to-source resistance TJ = 25°C 180 mΩ
Output offset voltage Zero input signal, G = 20 dB ±25 mV
PVDD OVERVOLTAGE (OV) PROTECTION
PVDD overvoltage-shutdown set 19.5 21 22.5 V
PVDD overvoltage-shutdown hysteresis 0.6 V
PVDD UNDERVOLTAGE (UV) PROTECTION
PVDD undervoltage-shutdown set 3.6 4 4.4 V
PVDD undervoltage-shutdown hysteresis 0.25 V
BYP
BYP pin voltage 6.4 6.9 7.4 V
POWER-ON RESET (POR)
PVDD voltage for POR 4.1 V
PVDD recovery hysteresis voltage for POR 0.3 V
OVERTEMPERATURE (OT) PROTECTION
Junction temperature for overtemperature shutdown 155 170 °C
Junction temperature overtemperature shutdown hystersis 15 °C
OVERCURRENT (OC) SHUTDOWN PROTECTION
Maximum current (peak output current) 2.4 A
STANDBY PIN
STANDBY pin current 0.1 0.2 µA
DC DETECT
DC detect threshold 2.9 V
DC detect step response time 700 ms
FAULT REPORT
FAULT pin output voltage for logic-level high (open-drain logic output) External 47-kΩ pullup resistor to 3.3 V 2.4 V
FAULT pin output voltage for logic-level low (open-drain logic output) External 47-kΩ pullup resistor to 3.3 V 0.5 V
LOAD DIAGNOSTICS
Resistance to detect a short from OUT pin(s) to PVDD or ground 200 Ω
Open-circuit detection threshold Including speaker wires 70 95 120 Ω
Short-circuit detection threshold Including speaker wires 0.9 1.2 1.5 Ω
I2C
SDA pin output voltage for logic-level high R(PU_I2C) = 4.7-kΩ pullup, supply voltage = 3.3 V or 5 V 2.4 V
SDA pin output voltage for logic-level low 3-mA sink current 0.4 V
Capacitance for SCL and SDA pins 10 pF
Capacitance for SDA pin STANDBY mode 30 pF