JAJSF33C August   2017  – February 2023 THS3491

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Bare Die Information
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics: VS = ±15 V
    6. 8.6 Electrical Characteristics: VS = ±7.5 V
    7. 8.7 Typical Characteristics: ±15 V
    8. 8.8 Typical Characteristics: ±7.5 V
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-Down (PD) Pin
      2. 9.3.2 Power-Down Reference (REF) Pin
      3. 9.3.3 Internal Junction Temperature Sense (TJ_SENSE) Pin
    4. 9.4 Device Functional Modes
      1. 9.4.1 Wideband Noninverting Operation
      2. 9.4.2 Wideband, Inverting Operation
      3. 9.4.3 Single-Supply Operation
      4. 9.4.4 Maximum Recommended Output Voltage
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Driving Capacitive Loads
      2. 10.1.2 Video Distribution
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 PowerPAD™ Integrated Circuit Package Design Considerations (DDA Package Only)
          1. 10.4.1.1.1 PowerPAD™ Integrated Circuit Package Layout Considerations
          2. 10.4.1.1.2 Power Dissipation and Thermal Considerations
      2. 10.4.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5 Electrical Characteristics: VS = ±15 V

at +VS = +15 V, –VS = –15 V, TA ≅ 25°C, RLOAD = 100 Ω to midsupply, noninverting gain (G) = 5 V/V, and RGT package: RF = 576 Ω, RG = 143 Ω, or DDA package: RF = 798 Ω, RG = 200 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Test Level(1)
AC PERFORMANCE
SSBW Small-signal bandwidth VO = 2 VPP, < 0.5-dB peaking 900 MHz C
LSBW Large-signal bandwidth VO = 10 VPP, < 1-dB peaking 320 MHz C
Bandwidth for 0.2-dB flatness VO = 2 VPP 350 MHz C
SR Slew rate (20% – 80%) VO = 20 VPP 8000 V/µs C
Overshoot and undershoot VO = 10-V step (input tr/tf = 1.0 ns) 1.5% C
tr/tf Rise and fall time VO = 10-V step (input tr/tf = 1.0 ns) 1.3 ns C
ts Settling time to 0.1% VO = 10-V step (input tr/tf = 1.0 ns) 7 ns C
HD2 Second-order harmonic distortion f = 20 MHz, VO = 10 VPP –78 dBc C
f = 50 MHz, VO = 10 VPP –76
f = 70 MHz, VO = 10 VPP –68
f = 100 MHz, VO = 10 VPP –60
f = 20 MHz, VO = 20 VPP –75
f = 50 MHz, VO = 20 VPP –65
f = 70 MHz, VO = 20 VPP –61
f = 100 MHz, VO = 20 VPP –51
HD3 Third-order harmonic distortion f = 20 MHz, VO = 10 VPP –81 dBc C
f = 50 MHz, VO = 10 VPP –75
f = 70 MHz, VO = 10 VPP –61
f = 100 MHz, VO = 10 VPP –51
f = 20 MHz, VO = 20 VPP –64
f = 50 MHz, VO = 20 VPP –55
f = 70 MHz, VO = 20 VPP –48
f = 100 MHz, VO = 20 VPP –47
IMD2 2nd-order two-tone intermodulation distortion f = 20 MHz, VO = 5 VPP per tone,
100-kHz tone spacing		 –79 dBc C
IMD3 3rd-order two-tone intermodulation distortion f = 20 MHz, VO = 5 VPP per tone,
100-kHz tone spacing		 –68 dBc C
en Input-referred voltage noise f ≥ 100 kHz 1.7 nV/√Hz C
inp Noninverting, input-referred current noise f ≥ 100 kHz 15 pA/√Hz C
inn Inverting, input-referred current noise f ≥ 100 kHz 20 pA/√Hz C
ZOUT Closed-loop output impedance f = 50 MHz 1 Ω C
DC PERFORMANCE
ZOL Open-loop transimpedance gain VO = ±10 V, RLOAD = 500 Ω 5 8 MΩ A1
VOS Input offset voltage DDA package only –2 1 2 mV A1
RGT package & DIE sales –2.5 1 2.5 mV A1
Input offset voltage drift(2) –40°C ≤ TJ ≤ +125°C 3 µV/°C B
IB+ Noninverting input bias current(3) –7 –2 7 µA A1
Noninverting input bias current drift(2) –40°C ≤ TJ ≤ +125°C –8 nA/°C B
IB- Inverting input bias current(3) –20 –7 20 µA A1
Inverting input bias current drift(2) –40°C ≤ TJ ≤ +125°C –116 nA/°C B
RFB_TRACE Internal trace resistance to feedback pin RGT only, pins 10 and 11 to pin 1 1.1 1.5 1.9 Ω A2
CMRR Common-mode rejection ratio f = DC 69 75 dB A1
INPUT
HRIN Headroom to either supply CMRR > 60 dB 4.1 4.3 V A2
ZIN+ Noninverting input impedance Closed-loop measurement  50 || 1.2 kΩ || pF C
ZIN- Inverting input impedance Open-loop measurement 8 15 18 Ω B
OUTPUT
HROUT Headroom to either supply 1.2 1.5 1.7 V A1
IoutMAX Maximum current output RLOAD = 24 Ω, VO = ±12.67 V, magnitude, both polarities 480 520 550 mA A2
IoutLINEAR Linear output current RLOAD = 24 Ω, VO = ±9.4 V,
ZOL > 1 MΩ, source and sink		 380 420 mA A2
IoutPEAK Peak output current in transition (transition peak at zero-crossing IOUT) VO = 0 V, RO < 0.5 Ω, magnitude, both polarities 500 540 mA B
ISC Output short-circuit current VS = ±9 V, VO = ±6 V, magnitude, both polarities 550 620 mA B
ZOUT DC output impedance Closed-loop (±50 mA) 0.17 Ω C
POWER SUPPLY
IQ Quiescent current VS = ±15 V, No load 16.1 16.7 17.3 mA A1
VS = ±16 V, No load 16.2 16.8 17.4 mA A2
VS = ±7 V, No load 15.2 15.8 16.3 mA A1
IQ TC VS = ±15 V, TJ = –40°C to +125°C,
No load		 5 µA/°C B
PSRR+ Positive power supply rejection ratio +VS ± 1.5 V, –VS 78 82 dB A1
PSRR– Negative power supply rejection ratio +VS, –VS ± 1.5 V 77 80 dB A1
POWER DOWN
REFRANGE REF pin voltage range Do NOT float the REF pin. –Vs GND     +Vs – 5 V V A2
IREF_BIAS REF pin bias current REF = 0 V, PD = REF + 3 V,
positive out of the pin.		 35 46 52 µA A2
VIL Disable voltage threshold REF = 0 V, guaranteed off below 0.8 V A1
VIH Enable voltage threshold REF = 0 V, guaranteed on above 1.5 V A1
PDLOW_BIAS PD pin low input bias current PD = REF = GND,
positive out of the pin.		 17 21 25 µA A2
PDHIGH_BIAS PD pin high input bias current PD = REF + 3 V, REF = GND,
positive out of the pin.		 –1 0 1 µA A2
IQ_OFF_+VS +Vs disabled supply current 650 780 880 µA A1
IQ_OFF_–VS –Vs disabled supply current 600 723 820 µA A2
tON Turnon time delay DC output to 90% of final value 50 ns C
tOFF Turnoff time delay DC output to 10% of final value 4 µs C
JUNCTION-TEMPERATURE SENSE, TJ_SENSE (QFN-16 ONLY, PIN 6)
TJ_SENSE 25°C value Device disabled (22°C to 32°C ATE ambient temperature)   0.915 1.06 1.15 V A2
TJ_SENSE temperature coefficient TJ = 0°C to 125°C 3.2 mV/°C B
TJ_SENSE input impedance Internally connected to REF pin 32.4 35 38 kΩ A2
(1) Test levels (all values set by characterization and simulation): (A1) 100% tested at ≈ 25°C for all devices, overtemperature limits by characterization and simulation; (A2) 100% tested at ≈ 25°C for packaged devices, not tested in production for die sales (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information;
(2) Input offset voltage drift and input bias current drift are average values calculated by taking data at the end points, computing the difference, and dividing by the temperature range.
(3) Current is considered positive out of the pin.