JAJSQA4I march   1994  – march 2021 TL16C550C

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 概要
  4. 3 Revision History
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Recommended Operating Conditions (Low Voltage - 3.3 nominal)
    3. 5.3  Recommended Operating Conditions (Standard Voltage - 5 V nominal)
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics (Low Voltage - 3.3 V nominal)
    6. 5.6  Electrical Characteristics (Standard Voltage - 5 V nominal)
    7. 5.7  System Timing Requirements
    8. 5.8  System Switching Characteristics
    9. 5.9  Baud Generator Switching Characteristics
    10. 5.10 Receiver Switching Characteristics
    11. 5.11 Transmitter Switching Characteristics
    12. 5.12 Modem Control Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Autoflow Control (see )
    2. 7.2 Auto-RTS (see )
    3. 7.3 Auto-CTS (see )
    4. 7.4 Enabling Autoflow Control and Auto-CTS
    5. 7.5 Auto-CTS and Auto-RTS Functional Timing
    6. 7.6 Functional Block Diagram
    7. 7.7 Principles of Operation
      1. 7.7.1  Accessible Registers
      2. 7.7.2  FIFO Control Register (FCR)
      3. 7.7.3  FIFO Interrupt Mode Operation
      4. 7.7.4  FIFO Polled Mode Operation
      5. 7.7.5  Interrupt Enable Register (IER)
      6. 7.7.6  Interrupt Identification Register (IIR)
      7. 7.7.7  Line Control Register (LCR)
      8. 7.7.8  Line Status Register (LSR)
      9. 7.7.9  Modem Control Register (MCR)
      10. 7.7.10 Modem Status Register (MSR)
      11. 7.7.11 Programming Baud Generator
      12. 7.7.12 Receiver Buffet Register (RBR)
      13. 7.7.13 Scratch Register
      14. 7.7.14 Transmitter Holding Register (THR)
  9. 8 Application Information
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.7.6 Interrupt Identification Register (IIR)

The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with most popular microprocessors.

The ACE provides four prioritized levels of interrupts:

  • Priority 1 − Receiver line status (highest priority).
  • Priority 2 − Receiver data ready or receiver character time-out.
  • Priority 3 − Transmitter holding register empty.
  • Priority 4 − Modem status (lowest priority).

When an interrupt is generated, the IIR indicates that an interrupt is pending and encodes the type of interrupt in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 7-3 and described in Table 7-5. Detail on each bit is as follows:

  • Bit 0: This bit is used either in a hardwire prioritized or polled interrupt system. When bit 0 is cleared, an interrupt is pending If bit 0 is set, no interrupt is pending.
  • Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 3.
  • Bit 3: This bit is always cleared in TL16C450 mode. In FIFO mode, bit 3 is set with bit 2 to indicate that a time-out interrupt is pending.
  • Bits 4 and 5: These two bits are not used (always cleared).
  • Bits 6 and 7: These bits are always cleared in TL16C450 mode. They are set when bit 0 of the FIFO control register is set.
Table 7-5 Interrupt Control Functions
INTERRUPT IDENTIFICATION REGISTER PRIORITY LEVEL INTERRUPT TYPE INTERRUPT SOURCE INTERRUPT RESET METHOD
BIT 3 BIT 2 BIT 1 BIT 0
0 0 0 1 None None None None
0 1 1 0 1 Receiver line status Overrun error, parity error, framing error, or break interrupt Read the line status register
0 1 0 0 2 Received data available Receiver data available in the TL16C450 mode or trigger level reached in the FIFO mode Read the receiver buffer register
1 1 0 0 2 Character time-out indication No characters have been removed from or input to the receiver FIFO during the last four character times, and there is at least one character in it during this time Read the receiver buffer register
0 0 1 0 3 Transmitter holding register empty Transmitter holding register empty Read the interrupt identification register(if source of interrupt) or writing into the transmitter holding register
0 0 0 0 4 Modem status Clear to send, data set ready, ring indicator, or data carrier detect Read the modem status register