JAJSQA4I march   1994  – march 2021 TL16C550C

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 概要
  4. 3 Revision History
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Recommended Operating Conditions (Low Voltage - 3.3 nominal)
    3. 5.3  Recommended Operating Conditions (Standard Voltage - 5 V nominal)
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics (Low Voltage - 3.3 V nominal)
    6. 5.6  Electrical Characteristics (Standard Voltage - 5 V nominal)
    7. 5.7  System Timing Requirements
    8. 5.8  System Switching Characteristics
    9. 5.9  Baud Generator Switching Characteristics
    10. 5.10 Receiver Switching Characteristics
    11. 5.11 Transmitter Switching Characteristics
    12. 5.12 Modem Control Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Autoflow Control (see )
    2. 7.2 Auto-RTS (see )
    3. 7.3 Auto-CTS (see )
    4. 7.4 Enabling Autoflow Control and Auto-CTS
    5. 7.5 Auto-CTS and Auto-RTS Functional Timing
    6. 7.6 Functional Block Diagram
    7. 7.7 Principles of Operation
      1. 7.7.1  Accessible Registers
      2. 7.7.2  FIFO Control Register (FCR)
      3. 7.7.3  FIFO Interrupt Mode Operation
      4. 7.7.4  FIFO Polled Mode Operation
      5. 7.7.5  Interrupt Enable Register (IER)
      6. 7.7.6  Interrupt Identification Register (IIR)
      7. 7.7.7  Line Control Register (LCR)
      8. 7.7.8  Line Status Register (LSR)
      9. 7.7.9  Modem Control Register (MCR)
      10. 7.7.10 Modem Status Register (MSR)
      11. 7.7.11 Programming Baud Generator
      12. 7.7.12 Receiver Buffet Register (RBR)
      13. 7.7.13 Scratch Register
      14. 7.7.14 Transmitter Holding Register (THR)
  9. 8 Application Information
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.7.5 Interrupt Enable Register (IER)

The IER enables each of the five types of interrupts (refer to Table 7-5) and enables INTRPT in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents of this register are summarized in Table 7-3 and are described in the following bullets.

  • Bit 0: When set, this bit enables the received data available interrupt.
  • Bit 1: When set, this bit enables the THRE interrupt.
  • Bit 2: When set, this bit enables the receiver line status interrupt.
  • Bit 3: When set, this bit enables the modem status interrupt.
  • Bits 4 through 7: These bits are not used (always cleared).