SLLSEF8C August   2013  – November 2014 TLK111


  1. Introduction
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. Pin Descriptions
    1. 2.1 Pin Layout
    2. 2.2 Serial Management Interface (SMI)
    3. 2.3 MAC Data Interface
    4. 2.4 10Mbs and 100Mbs PMD Interface
    5. 2.5 Clock Interface
    6. 2.6 LED Interface
    7. 2.7 JTAG Interface
    8. 2.8 Reset and Power Down
    9. 2.9 Power and Bias Connections
  3. Hardware Configuration
    1. 3.1  Bootstrap Configuration
    2. 3.2  Power Supply Configuration
      1. 3.2.1 Single Supply Operation
      2. 3.2.2 Dual Supply Operation
      3. 3.2.3 Variable IO Voltage
    3. 3.3  IO Pins Hi-Z State During Reset
    4. 3.4  Auto-Negotiation
    5. 3.5  Auto-MDIX
    6. 3.6  PHY Address
    7. 3.7  MII Isolate Mode
    8. 3.8  Software Strapping Mode
    9. 3.9  LED Interface
    10. 3.10 Multi-Configurable LED (MLED)
    11. 3.11 Loopback Functionality
      1. 3.11.1 Near-End Loopback
      2. 3.11.2 Far-End Loopback
    12. 3.12 BIST
    13. 3.13 Cable Diagnostics
      1. 3.13.1 TDR
      2. 3.13.2 ALCD
  4. Interfaces
    1. 4.1 Media Independent Interface (MII)
    2. 4.2 Reduced Media Independent Interface (RMII)
    3. 4.3 Serial Management Interface
      1. 4.3.1 Extended Address Space Access
        1. Write Address Operation
        2. Read Address Operation
        3. Write (no post increment) Operation
        4. Read (no post increment) Operation
        5. Write (post increment) Operation
        6. Read (post increment) Operation
  5. Architecture
    1. 5.1 100Base-TX Transmit Path
      1. 5.1.1 MII Transmit Error Code Forwarding
      2. 5.1.2 4-Bit to 5-Bit Encoding
      3. 5.1.3 Scrambler
      4. 5.1.4 NRZI and MLT-3 Encoding
      5. 5.1.5 Digital to Analog Converter
    2. 5.2 100Base-TX Receive Path
      1. 5.2.1  Analog Front End
      2. 5.2.2  Adaptive Equalizer
      3. 5.2.3  Baseline Wander Correction
      4. 5.2.4  NRZI and MLT-3 Decoding
      5. 5.2.5  Descrambler
      6. 5.2.6  5B/4B Decoder and Nibble Alignment
      7. 5.2.7  Timing Loop and Clock Recovery
      8. 5.2.8  Phase-Locked Loops (PLL)
      9. 5.2.9  Link Monitor
      10. 5.2.10 Signal Detect
      11. 5.2.11 Bad SSD Detection
    3. 5.3 10Base-T Receive Path
      1. 5.3.1 10M Receive Input and Squelch
      2. 5.3.2 Collision Detection
      3. 5.3.3 Carrier Sense
      4. 5.3.4 Jabber Function
      5. 5.3.5 Automatic Link Polarity Detection and Correction
      6. 5.3.6 10Base-T Transmit and Receive Filtering
      7. 5.3.7 10Base-T Operational Modes
    4. 5.4 Auto Negotiation
      1. 5.4.1 Operation
      2. 5.4.2 Initialization and Restart
      3. 5.4.3 Configuration Bits
      4. 5.4.4 Next Page Support
    5. 5.5 Link Down Functionality
    6. 5.6 IEEE 1588 Precision Timing Protocol Support
  6. Reset and Power Down Operation
    1. 6.1 Hardware Reset
    2. 6.2 Software Reset
    3. 6.3 Power Down/Interrupt
      1. 6.3.1 Power Down Control Mode
      2. 6.3.2 Interrupt Mechanisms
    4. 6.4 Power Save Modes
  7. Design Guidelines
    1. 7.1 TPI Network Circuit
    2. 7.2 Clock In (XI) Requirements
      1. 7.2.1 Oscillator
      2. 7.2.2 Crystal
    3. 7.3 Thermal Vias Recommendation
  8. Register Block
    1. 8.1  Register Definition
      1. 8.1.1  Basic Mode Control Register (BMCR)
      2. 8.1.2  Basic Mode Status Register (BMSR)
      3. 8.1.3  PHY Identifier Register 1 (PHYIDR1)
      4. 8.1.4  PHY Identifier Register 2 (PHYIDR2)
      5. 8.1.5  Auto-Negotiation Advertisement Register (ANAR)
      6. 8.1.6  Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
      7. 8.1.7  Auto-Negotiate Expansion Register (ANER)
      8. 8.1.8  Auto-Negotiate Next Page Transmit Register (ANNPTR)
      9. 8.1.9  Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
      10. 8.1.10 Software Strap Control register 1 (SWSCR1)
      11. 8.1.11 Software Strap Control register 2 (SWSCR2)
      12. 8.1.12 Software Strap Control Register 3 (SWSCR3)
      13. 8.1.13 Extended Register Addressing
        1. Register Control Register (REGCR)
        2. Address or Data Register (ADDAR)
      14. 8.1.14 Fast Link Down Status Register
      15. 8.1.15 PHY Status Register (PHYSTS)
      16. 8.1.16 PHY Specific Control Register (PHYSCR)
      17. 8.1.17 MII Interrupt Status Register 1 (MISR1)
      18. 8.1.18 MII Interrupt Status Register 2 (MISR2)
      19. 8.1.19 False Carrier Sense Counter Register (FCSCR)
      20. 8.1.20 Receiver Error Counter Register (RECR)
      21. 8.1.21 BIST Control Register (BISCR)
      22. 8.1.22 RMII Control and Status Register (RCSR)
      23. 8.1.23 LED Control Register (LEDCR)
      24. 8.1.24 PHY Control Register (PHYCR)
      25. 8.1.25 10Base-T Status/Control Register (10BTSCR)
      26. 8.1.26 BIST Control and Status Register 1 (BICSR1)
      27. 8.1.27 BIST Control and Status Register2 (BICSR2)
    2. 8.2  Cable Diagnostic Control Register (CDCR)
    3. 8.3  PHY Reset Control Register (PHYRCR)
    4. 8.4  Multi LED Control register (MLEDCR)
    5. 8.5  IEEE1588 Precision Timing Pin Select (PTPPSEL)
    6. 8.6  IEEE1588 Precision Timing Configuration (PTPCFG)
    7. 8.7  TX_CLK Phase Shift Register (TXCPSR)
    8. 8.8  Power Back Off Control Register (PWRBOCR)
    9. 8.9  Voltage Regulator Control Register (VRCR)
    10. 8.10 Cable Diagnostic Configuration/Result Registers
      1. 8.10.1  ALCD Control and Results 1 (ALCDRR1)
      2. 8.10.2  Cable Diagnostic Specific Control Registers (CDSCR1 - CDSCR4)
      3. 8.10.3  Cable Diagnostic Location Results Register 1 (CDLRR1)
      4. 8.10.4  Cable Diagnostic Location Results Register 2 (CDLRR2)
      5. 8.10.5  Cable Diagnostic Location Results Register 3 (DDLRR3)
      6. 8.10.6  Cable Diagnostic Location Results Register 4 (CDLRR4)
      7. 8.10.7  Cable Diagnostic Location Results Register 5 (CDLRR5)
      8. 8.10.8  Cable Diagnostic Amplitude Results Register 1 (CDARR1)
      9. 8.10.9  Cable Diagnostic Amplitude Results Register 2 (CDARR2)
      10. 8.10.10 Cable Diagnostic Amplitude Results Register 3 (CDARR3)
      11. 8.10.11 Cable Diagnostic Amplitude Results Register 4 (CDARR4)
      12. 8.10.12 Cable Diagnostic Amplitude Results Register 5 (CDARR5)
      13. 8.10.13 Cable Diagnostic General Results Register (CDGRR)
      14. 8.10.14 ALCD Control and Results 2 (ALCDRR2)
      15. 8.10.15 ALCD Control and Results 3 (ALCDRR3)
  9. Electrical Specifications
    1. 9.1 Absolute Maximum Ratings
    2. 9.2 Handling Ratings
    3. 9.3 Recommended Operating ConditionsRedundant row "Power dissipation 200 mW"
    4. 9.4 48-Pin Industrial Device Thermal Characteristics
    5. 9.5 48-Pin Extended Temperature (125°C) Device Thermal Characteristics
    6. 9.6 DC Characteristics, VDD_IO DC Characteristics, SD_IN
    7. 9.7 DC Characteristics
    8. 9.8 Power Supply Characteristics
      1. 9.8.1 Active Power, Single Supply Operation
      2. 9.8.2 Active Power, Dual Supply Operation
      3. 9.8.3 Power-Down Power
    9. 9.9 AC Specifications
      1. 9.9.1  Power Up Timing
      2. 9.9.2  Reset Timing
      3. 9.9.3  MII Serial Management Timing
      4. 9.9.4  100Mb/s MII Transmit Timing
      5. 9.9.5  100Mb/s MII Receive Timing
      6. 9.9.6  100Base-TX Transmit Packet Latency Timing
      7. 9.9.7  100Base-TX Transmit Packet Deassertion Timing
      8. 9.9.8  100Base-TX Transmit Timing (tR/F and Jitter)
      9. 9.9.9  100Base-TX Receive Packet Latency Timing
      10. 9.9.10 100Base-TX Receive Packet Deassertion Timing
      11. 9.9.11 10Mbs MII Transmit Timing
      12. 9.9.12 10Mb/s MII Receive Timing
      13. 9.9.13 10Base-T Transmit Timing (Start of Packet)
      14. 9.9.14 10Base-T Transmit Timing (End of Packet)
      15. 9.9.15 10Base-T Receive Timing (Start of Packet)
      16. 9.9.16 10Base-T Receive Timing (End of Packet)
      17. 9.9.17 10Mb/s Jabber Timing
      18. 9.9.18 10Base-T Normal Link Pulse Timing
      19. 9.9.19 Auto-Negotiation Fast Link Pulse (FLP) Timing
      20. 9.9.20 100Base-TX Signal Detect Timing
      21. 9.9.21 100Mbs Loopback Timing
      22. 9.9.22 10Mbs Internal Loopback Timing
      23. 9.9.23 RMII Transmit Timing
      24. 9.9.24 RMII Receive Timing
      25. 9.9.25 Isolation Timing
      26. 9.9.26 25MHz_OUT Clock Timing
  10. 10Revision History, Revision A



5 Architecture

The TLK111 Fast Ethernet transceiver is a physical layer core for Ethernet 100Base-TX and 10Base-T applications. The TLK111 contains all the active circuitry required to implement the physical layer functions to transmit and receive data on standard CAT 3 and 5 unshielded twisted pair. The core supports the IEEE 802.3 Standard Fast Media Independent Interface (MII), as well as the Reduced Media Independent Interface (RMII), for direct connection to a MAC/Switch port.

The TLK111 uses mixed signal processing to perform equalization, data recovery and error correction to achieve robust and low power operation over the existing CAT 5 twisted pair wiring. The TLK111 architecture not only meets the requirements of IEEE802.3, but maintains a high level of margin over the IEEE requirements for NEXT, Alien and External noise.

phy_arch_lls931.gifFigure 5-1 PHY Architecture

5.1 100Base-TX Transmit Path

In 100Base-TX, the MAC feeds the 100Mbps transmit data in 4-bit wide nibbles through the MII interface. The data is encoded into 5-bit code groups, encapsulated with control code symbols and serialized. The control-code symbols indicate the start and end of the frame and code other information such as transmit errors. When no data is available from the MAC, IDLE symbols are constantly transmitted. The serialized bit stream is fed into a scrambler. The scrambled data stream passes through an NRZI encoder and then through an MLT3 encoder. Finally, it is fed to the DAC and transmitted through one of the twisted pairs of the cable.

5.1.1 MII Transmit Error Code Forwarding

According to IEEE 802.3:

“If TX_EN is de-asserted on an odd nibble boundary, PHY should extend TX_EN by one TX_CLK cycle and behave as if TX_ER were asserted during that cycle”.

The TLK111 supports Error Forwarding in MII transmission from the MAC to the PHY. Error forwarding allows adding information to the frame to be used as an error code between the 2 MACs. The error code informs the receiving MAC on the link partner side of the reason for the error from the transmitting side. If the MAC transmits an odd number of nibbles, an additional error nibble is added to the transmitted frame just before the end of the transmission.

To turn off Transmit Error Forwarding, write to bit 1 of register SWSCR2 (0x000A). If Error Forwarding is disabled, delivered packets contain either odd or even numbers of nibbles.

In Figure 5-2, Error Code Forwarding functionality is illustrated. The wave diagram demonstrates MAC’s transmitted signals in one side and MAC’s reception signals on link partner side.

tx_cd_error_lls901.gifFigure 5-2 Transmit Code Error Forwarding Diagram

5.1.2 4-Bit to 5-Bit Encoding

The transmit data that is received from the MAC first passes through the 4-Bit to 5-Bit encoder. This block encodes 4-bit nibble into 5-bit code-groups according to the Table 5-1. Each 4-bit data nibble is mapped to 16 of the 32 possible code-groups. The remaining 16 code-groups are either used for control information or they are considered as not valid.

The code-group encoder substitutes the first 8-bits of the MAC preamble with a J/K code-group pair (11000 10001) upon transmission. The code-group encoder continues to replace subsequent 4-bit preamble and data nibbles with corresponding 5-bit code-groups. At the end of the transmit packet, upon the de-assertion of Transmit Enable signal from the MAC, the code-group encoder adds the T/R code-group pair (01101 00111) indicating the end of the frame.

After the T/R code-group pair, the code-group encoder continuously adds IDLEs into the transmit data stream until the next transmit packet is detected.

Table 5-1 4-Bit to 5-Bit Code Table

4-Bit Code Symbol 5-Bit Code Receiver Interpretation
0000 0 11110 Data
0001 1 01001
0010 2 10100
0011 3 10101
0100 4 01010
0101 5 01011
0110 6 01110
0111 7 01111
1000 8 10010
1001 9 10011
1010 A 10110
1011 B 10111
1100 C 11010
1101 D 11011
1110 E 11100
1111 F 11101
DESCRIPTION Symbol(1) 5-Bit Code
Inter-Packet IDLE I 11111 IDLE
First nibble of SSD J 11000 First nibble of SSD, translated to "0101" following /I/ (IDLE), else RX_ER asserted high
Second nibble of SSD K 10001 Second nibble of SSD, translated to "0101" following /J/, else RX_ER asserted high
First nibble of ESD T 01101 First nibble of ESD, causes de-assertion of CRS if followed by /R/, else assertion of RX_ER
Second nibble of ESD R 00111 Second nibble of ESD, causes de-assertion of CRS if following /T/, else assertion of RX_ER
Transmit Error Symbol H 00100 RX_ER
Invalid Symbol V 00000 INVALID
RX_ER asserted high If during RX_DV
V 00001
V 00010
V 00011
V 00101
V 00110
V 01000
V 01100
(1) Control code-groups I, J, K, T and R in data fields will be mapped as invalid codes, together with RX_ER asserted.

5.1.3 Scrambler

The purpose of the scrambler is to flatten the power spectrum of the transmitted signal, thus reduce EMI. The scrambler seed is generated with reference to the PHY address so that multiple PHYs that reside within the system will not use the same scrambler sequence.

5.1.4 NRZI and MLT-3 Encoding

To comply with the TP-PMD standard for 100Base-TX transmission over CAT-5 unshielded twisted pair cable, the scrambled data must be NRZI encoded. The serial binary data stream output from the NRZI encoder is further encoded to MLT-3. MLT-3 is a tri-level code where a change in the logic level represents a code bit '1' and the logic output remaining at the same level represents a code bit '0'.

5.1.5 Digital to Analog Converter

The multipurpose programmable transmit Digital to Analog Converter (DAC) receives digital coded symbols and generates filtered analog symbols to be transmitted on the line. In 100B-TX the DAC applies a low-pass shaping filter to minimize EMI. The DAC is designed to improve the return loss requirements and enable the use of low-cost transformers.

Digital pulse-shape filtering is also applied in order to conform to the pulse masks defined by standard and to reduce EMI and high frequency signal harmonics.

5.2 100Base-TX Receive Path

In 100B-TX, the ADC sampled data is passed to an adaptive equalizer. The adaptive equalizer drives the received symbols to the MLT3 decoder. The decoded NRZ symbols are transferred to the descrambler block for descrambling and deserialization.

5.2.1 Analog Front End

The Receiver Analog Front End (AFE) resides in front of the 100B-TX receiver. The AFE consists of an Analog to Digital Converter (ADC), receive filters and a Programmable Gain Amplifier (PGA).

The ADC samples the input signal at the 125MHz clock recovered by the timing loop and feeds the data into the adaptive equalizer. The ADC is designed to optimize the SNR performance at the receiver input while maintaining high power-supply rejection ratio and low power consumption. There is only one ADC in the TLK111, which receives the analog input data from the relevant cable pair, according to MDI-MDIX resolution.

The PGA, digitally controlled by the adaptive equalizer, fully uses the dynamic range of the ADC by adjusting the incoming-signal amplitude. Generally, the PGA attenuates short-cable strong signals and amplifies long-cable weak signals.

5.2.2 Adaptive Equalizer

The adaptive equalizer removes Inter-Symbol Interference (ISI) from the received signal introduced by the channel and analog Tx/Rx filters. The TLK111 includes both Feed Forward Equalization (FFE) and Decision Feedback Equalization (DFE). The combination of both adaptive modules with the adaptive gain control results in a powerful equalizer that can eliminate ISI and compensate for cable attenuation for longer-reach cables. In addition, the Equalizer includes a Shift Gear Step mechanism to provide fast convergence on the one hand and small residual-adaptive noise in steady state on the other hand.

5.2.3 Baseline Wander Correction

The DC offset of the transmitted signal is shifted down or up based on the polarity of the transmitted data because the MLT-3 data is coupled onto the CAT 5 cable through a transformer that is high-pass in nature. This phenomenon is called Baseline wander. To prevent corruption of the received data because of this phenomenon, the receiver corrects the baseline wander and can receive the ANSI TP-PMD-defined "killer packet" with no bit errors.

5.2.4 NRZI and MLT-3 Decoding

The TLK111 decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary NRZI data. The NRZI-to-NRZ decoder is used to present NRZ-formatted data to the descrambler.

5.2.5 Descrambler

The descrambler is used to descramble the received NRZ data. The data is further deserialized and the parallelized data is aligned to 5-bit code-groups and mapped into 4-bit nibbles. At initialization, the 100B-TX descrambler uses the IDLE-symbols sequence to lock on the far-end scrambler state. During that time, neither data transmission nor reception is enabled. After the far-end scrambler state is recovered, the descrambler constantly monitors the data and checks whether it still synchronized. If, for any reason, synchronization is lost, the descrambler tries to re-acquire synchronization using the IDLE symbols.

5.2.6 5B/4B Decoder and Nibble Alignment

The code-group decoder functions as a look up table that translates incoming 5-bit code-groups into 4-bit nibbles. The code-group decoder first detects the Start of Stream Delimiter (SSD) /J/K/ code-group pair preceded by IDLE code-groups at the start of a packet. Once the code group alignment is determined, it is stored and used until the next start-of-frame. The decoder replaces the /J/K/ with the MAC preamble. Specifically, the /J/K/ 10-bit code-group pair is replaced by the nibble pair (0101 0101). All subsequent 5-bit code-groups are converted to the corresponding 4-bit nibbles for the duration of the entire packet. This conversion ceases upon the detection of the /T/R/ code-group pair denoting the End-of-Stream Delimiter (ESD) or with the reception of a minimum of two IDLE code-groups.

5.2.7 Timing Loop and Clock Recovery

The receiver must lock on the far-end transmitter clock in order to sample the data at the optimum timing. The timing loop recovers the far-end clock frequency and offset from the received data samples and tracks instantaneous phase drifts caused by timing jitter.

The TLK111 has a robust adaptive-timing loop (Tloop) mechanism that is responsible for tracking the Far-End TX clock and adjusting the AFE sampling point to the incoming signal. The Tloop implements an advanced tracking mechanism that when combined with different available phases, always keeps track of the optimized sampling point for the data, and thus offers a robust RX path,tolerant to both PPM and Jitter. The TLK111 is capable of dealing with PPM and jitter at levels far higher than those defined by the standard.

5.2.8 Phase-Locked Loops (PLL)

In 10B-T the digital phase lock loop (DPLL) function recovers the far-end link-partner clock from the received Manchester signal. The DPLL is able to combat clock jitter of up to ±18ns and frequency drifts of ±500ppm between the local PHY clock and the far-end clock. The DPLL feeds the decoder with a decoded serial bit stream.

The integrated analog Phase-Locked Loop (PLL) provides the clocks to the analog and digital sections of the PHY. The PLL is driven by an external reference clock (sourced at the XI,XO pins with a crystal oscillator, or at XI with an external reference clock).

5.2.9 Link Monitor

The TLK111 implements the link monitor State Machine (SM) as defined by the IEEE 802.3 100Base-TX Standard. In addition, the TLK111 enables several add-ons to the link monitor SM activated by configuration bits. The new add-ons include the recovery state which enables the PHY to attempt recovery in the event of a temporary energy-loss situation before entering the LINK_FAIL state, thus restarting the whole link establishment procedure. This sequence allows significant reduction of the recovery time in scenarios where the link loss is temporal.

In addition, the link monitor SM enables moving to the LINK_DOWN state based on descrambler synchronization failure and not only on Signal_Status indication, which shortens the drop-link down time. These add-ons are supplementary to the IEEE standard and are bypassed by default.

5.2.10 Signal Detect

The signal detect function of the TLK111 is incorporated to meet the specifications mandated by the ANSIFDDI TP-PMD Standard as well as the IEEE 802.3 100Base-TX Standard for both voltage thresholds and timing parameters.

The energy-detector module provides signal-strength indication in various scenarios. Because it is based on an IIR filter, this robust energy detector has excellent reaction time and reliability. The filter output is compared to predefined thresholds in order to decide the presence or absence of an incoming signal.

The energy detector also implements hysteresis to avoid jittering in signal-detect indication. In addition it has fully-programmable thresholds and listening-time periods, enabling shortening of the reaction time if required.

5.2.11 Bad SSD Detection

A Bad Start of Stream Delimiter (Bad SSD) is any transition from consecutive idle code-groups to non-idle code-groups which is not prefixed by the code-group pair /J/K. If this condition is detected, the TLK111 asserts RX_ER, and presents RXD[3:0] = 1110 to the MII for the cycles that correspond to received 5B code-groups until at least two IDLE code groups are detected. In addition, the FCSCR register (0x14h) is incremented by one for every error in the nibble.

When at least two IDLE code groups are detected, RX_ER and CRS are de-asserted.

5.3 10Base-T Receive Path

In 10B-T, after the far-end clock is recovered, the received Manchester symbols pass to the Manchester decoder. The serial decoded bit stream is aligned to the start of the frame, de-serialized to 4-bit wide nibbles and sent to the MAC through the MII.

5.3.1 10M Receive Input and Squelch

The squelch feature determines when valid data is present on the differential receive inputs. The TLK111 implements a squelch to prevent impulse noise on the receive inputs from being mistaken for a valid signal. Squelch operation is independent of the 10Base-T operating mode. The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.3 10Base-T standard) to determine the validity of data on the twisted-pair inputs.

The signal at the start of a packet is checked by the squelch, and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) are rejected. When this first squelch level is exceeded correctly, the opposite squelch level must then be exceeded no earlier than 50ns. Finally, the signal must again exceed the original squelch level no earlier than 50ns to qualify as a valid input waveform, and not be rejected. This checking procedure results in the typical loss of three preamble bits at the beginning of each packet. When the transmitter is operating, five consecutive transitions are checked before indicating that valid data is present. At this time, the squelch circuitry is reset.

5.3.2 Collision Detection

When in Half-Duplex mode, a 10Base-T collision is detected when receive and transmit channels are active simultaneously. Collisions are reported by the COL signal on the MII.

The COL signal remains set for the duration of the collision. If the PHY is receiving when a collision is detected, it is reported immediately (through the COL pin).

5.3.3 Carrier Sense

Carrier Sense (CRS) may be asserted due to receive activity after valid data is detected via the squelch function. For 10Mb/s Half Duplex operation, CRS is asserted during either packet transmission or reception. For 10Mb/s Full Duplex operation, CRS is asserted only during receive activity.

CRS is de-asserted following an end-of-packet.

5.3.4 Jabber Function

Jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length, usually due to a fault condition. The jabber function monitors the TLK111 output and disables the transmitter if it attempts to transmit a packet of longer than legal size. A jabber timer monitors the transmitter and disables the transmission if the transmitter is active for approximately 100ms.

When disabled by the Jabber function, the transmitter stays disabled for the entire time that the ENDEC module's internal transmit enable is asserted. This signal must be de-asserted for approximately 500ms (the unjab time) before the Jabber function re-enables the transmit outputs.

The Jabber function is only available and active in 10Base-T mode.

5.3.5 Automatic Link Polarity Detection and Correction

Swapping the wires within the twisted pair causes polarity errors. Wrong polarity affects the 10B-T PHYs. The 100B-TX is immune to polarity problems because it uses MLT3 encoding. The 10B-T automatically detects reversed polarity according to the received link pulses or data.

5.3.6 10Base-T Transmit and Receive Filtering

External 10Base-T filters are not required when using the TLK111, because the required signal conditioning is integrated into the device. Only isolation transformers and impedance matching resistors are required for the 10Base-T transmit and receive interface. The internal transmit filtering ensures that all the harmonics in the transmit signal are attenuated by at least 30dB.

5.3.7 10Base-T Operational Modes

The TLK111 has two basic 10Base-T operational modes:

  • Half Duplex mode – In Half Duplex mode the TLK111 functions as a standard IEEE 802.3 10Base-T transceiver supporting the CSMA/CD protocol.
  • Full Duplex mode – In Full Duplex mode the TLK111 is capable of simultaneously transmitting and receiving without asserting the collision signal. The TLK111 10Mbs ENDEC is designed to encode and decode simultaneously.

5.4 Auto Negotiation

The auto-negotiation function, described in detail in IEEE802.3 chapter 28, provides the means to exchange information between two devices and automatically configure both of them to take maximum advantage of their abilities.

5.4.1 Operation

Auto negotiation uses the 10B-T link pulses to encapsulate the transmitted data in a sequence of pulses, also referred to as a Fast Link Pulses (FLP) burst. The FLP Burst consists of a series of closely spaced 10B-T link integrity test pulses that form an alternating clock/data sequence. Extraction of the data bits from the FLP Burst yields a Link Code Word that identifies the operational modes supported by the remote device, as well as some information used for the auto negotiation function’s handshake mechanism.

The information exchanged between the devices during the auto-negotiation process consists of the devices' abilities such as duplex support and speed. This information allows higher levels of the network (MAC) to send to the other link partner vendor-specific data (via the Next Page mechanism, see below), and provides the mechanism for both parties to agree on the highest performance mode of operation.

When auto negotiation has started, the TLK111 transmits FLP on one twisted pair and listens on the other, thus trying to find out whether the other link partner supports the auto negotiation function as well. The decision on what pair to transmit/listen depends on the MDI/MDI-X state. If the other link partner activates auto negotiation, then the two parties begin to exchange their information. If the other link partner is a legacy PHY or does not activate the auto negotiation, then the TLK111 uses the parallel detection function, as described in IEEE802.3 chapters 40 and 28, to determine 10B-T or 100B-TX operation modes.

5.4.2 Initialization and Restart

The TLK111 initiates the auto negotiation function if it is enabled through the configuration jumper options AN_EN, AN_1 and AN_0 (pins 34,35,36) and one of the following events have happened:

  1. Hardware reset de-assertion
  2. Software reset (via register)
  3. Auto negotiation restart (via register BMCR (0x0000h) bit 9)
  4. Power-up sequence (via register BMCR (0x0000h) bit 11)

The auto-negotiation function is also initiated when the auto-negotiation enable bit is set in register BMCR (0x0000h) bit 12 and one of the following events has happened:

  1. Software restart
  2. Transitioning to link_fail state, as described in IEEE802.3

To disable the auto-negotiation function during operation, clear register BMCR (0x0000h) bit 12. During operation, setting/resetting this register does not affect the TLK111 operation. For the changes to take place, issue a restart command through register BMCR (0x0000h) bit 9.

5.4.3 Configuration Bits

The auto-negotiation options can be configured through the configuration bits AN_EN, AN_1 and AN_0 as described in Table 5-2. The configuration bits allow the user to disable/enable the auto negotiation, and select the desirable advertisement features.

During hardware/software reset, the values of these configuration bits are latched into the auto-negotiation registers and available for user read and modification.

Table 5-2 Auto-Negotiation Modes

AN_EN AN_1 AN_0 Forced Mode
0 0 0 10Base-T, Half-Duplex
0 0 1 10Base-T, Full-Duplex
0 1 0 100Base-TX, Half-Duplex
0 1 1 100Base-TX, Full-Duplex
AN_EN AN_1 AN_0 Advertised Mode
1 0 0 10Base-T, Half or Full-Duplex
1 0 1 100Base-TX, Half or Full-Duplex
1 1 0 10Base-T,Half-Duplex
100Base-TX, Half-Duplex
1 1 1 10Base-T,Half or Full-Duplex
100Base-TX, Half or Full-Duplex

5.4.4 Next Page Support

The TLK111 supports the optional feature of the transmission and reception of auto-negotiation additional (vendor specific) next pages.

If next pages are needed, the user must set register ANAR(0x0004h) bit 15 to '1'. The next pages are then sent and received through registers ANNPTR(0x0007h) and ANLNPTR(0x0008h), respectively. The user must poll register ANER(0x0006h) bit 1 to check whether a new page has been received, and then read register ANLNPTR for the received next page's content. Only after register ANLNPTR is read may the user write to register ANNPTR the next page to be transmitted. After register ANNPTR is written, new next pages overwrite the contents of register ANLNPTR.

If register ANAR(0x0004h) bit 15 is set, then the next page sequence is controlled by the user, meaning that the auto-negotiation function always waits for register ANNPTR to be written before transmitting the next page.

If additional user-defined next pages are transmitted and the link partner has more next pages to send, it is the user's responsibility to keep writing null pages (of value 0x2001) to register ANNPTR until the link partner notifies that it has sent its last page (by setting bit 15 of its transmitted next page to zero).

5.5 Link Down Functionality

The TLK111 includes advanced link-down capabilities that support various real-time applications. The link-down mechanism of the TLK111 is configurable and includes enhanced modes that allow extremely fast reaction times to link-drops.

link_loss_lls901.gifFigure 5-3 TLK111 Link Loss Mechanism

As described in Figure 5-3, the TLK111 link loss mechanism is based on a time window search period, in which the signal behavior is monitored. The T1 window is set by default to reduce typical link-drops to less than 1ms.

The TLK111 supports enhanced modes that shorten the window called Fast Link Down mode. In this mode, which can be configured in Software Strap Control Register 3 (SWSCR3), address 0x000B, bits 3:0, the T1 window is shortened significantly, in most cases less than 10µs. In this period of time there are several criteria allowed to generate link loss event and drop the link:

  1. Count RX Error in the MII interface: When a predefined number of 32 RX Error occurrences in time window of 10µs is reached the link will drop.
  2. Count MLT3 Errors at the signal processing output (100BT uses MLT3 coding, and when a violation of this coding is detected, an MLT3 error is declared). When a predefined number of 20 errors occurrences in 10µs is reached the link will drop.
  3. Count Low Signal Quality Threshold crossing (When the signal quality is under a certain threshold that allows proper link conditions). When a predefined number of 20 occurrences in 10µs is reached, the link will drop.
  4. Signal/Energy loss indications. When Energy detector indicates Energy Loss, the link will be dropped. Typical reaction time is 10µs.

The Fast Link Down functionality allows the use of each of these options separately or in any combination. Note that since this mode enables extremely quick reaction time, it is more exposed to temporary bad link-quality scenarios.

5.6 IEEE 1588 Precision Timing Protocol Support

The TLK111supports an IEEE 1588 indication pulse at the SFD (start frame delimiter) for the RX and TX paths in 100BT mode. The pulse can be delivered to various pins as configured by register 0x3e. The pulse indicates the actual time the symbol is presented on the lines (for TX), or the first bit where the /J/ symbol is received (RX). Exact timing of the pulse can be adjusted using register 0x3f. Each increment of phase value is an 8ns step.

tlk10xL_td_ieee1588.gifFigure 5-4 IEEE 1588 Message Timestamp Point