SLLSEF8C August 2013 – November 2014 TLK111
The Media Independent Interface (MII) is a synchronous 4-bit wide nibble data interface that connects the PHY to the MAC in 100B-TX and 10B-T modes. The MII is fully compliant with IEEE802.3-2002 clause 22.
The MII signals are summarized below.
|Data signals||TXD [3:0]|
|Transmit and receive-valid signals||TX_EN|
|Line-status signals||CRS (carrier sense)|
Figure 4-1 shows the MII-mode signals.
The Isolate bit (BMCR register bit 10), defined in IEEE802.3-2002, electrically isolates the PHY from the MII (if set, all transactions on the MII interface are ignored by the PHY).
Additionally, the MII interface includes the carrier sense signal CRS, as well as a collision detect signal COL. The CRS signal asserts to indicate the reception of data from the network or as a function of transmit data in Half Duplex mode. The COL signal asserts as an indication of a collision which can occur during half-duplex operation when both transmit and receive operation occur simultaneously.
TLK111 incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII specification (rev1.2) from the RMII consortium. The purpose of this interface is to provide a low cost alternative to the IEEE 802.3u MII as specified in Clause 22. Architecturally, the RMII specification provides an additional reconciliation layer on either side of the MII, but can be implemented in the absence of an MII.
The RMII specification has the following characteristics:
In this mode, data transfers two bits at a time using the 50MHz RMII reference clock for both transmit and receive. RMII mode uses the following pins:
|XI (RMII reference clock is 50MHz)||34|
Data on TXD [1:0] are latched at the PHY with reference to the reference-clock edges on the XI pin. Data on RXD [1:0] are latched at the MAC with reference to the same reference clock edges on the XI pin. The RMII operates at the same speed (50MHz) in both 10B-T and 100B-TX. In 10B-T the data is 10 times slower than the reference clock, so transmit data is sampled every 10 clocks. Likewise, receive data is generated on every 10th clock so that an attached MAC device can sample the data every 10 clocks.
In addition, RMII mode supplies an RX_DV signal which allows a simpler method of recovering receive data without the need to separate RX_DV from the CRS_DV indication. RX_ER is also supported even though not required by RMII spec (The TLK111 supports optional use of RX_ER and RX_DV in RMII as an extra feature). RMII mode requires a 50MHz oscillator connected to the device XI pin.
The TLK111 supports a special mode called “RMII receive clock” mode. This mode, which is not part of the RMII specification, allows synchronization of the MAC-PHY RX interface. In this mode, the PHY generates a recovered 50MHz clock through the RX_CLK pin and synchronizes the RXD[1:0], CRS_DV, RX_DV and RX_ER signals to this clock. Setting register 0x000A bit  is required to activate this mode.
Figure 4-2 describes the RMII signals connectivity between the TLK111 and any MAC device.
RMII function includes a programmable elastic buffer to adjust for the frequency differences between the reference clock and the recovered receive clock. The programmable elastic buffer minimizes internal propagation delay based on expected maximum packet size and clock accuracy.
Table 4-1 indicates how to program the buffer FIFO based on the expected max packet size and clock accuracy. It assumes that the RMII reference clock and the far-end transmitter clock have the same accuracy.
|Start Threshold RBR[1:0]||Latency Tolerance||Recommended packet size at ±50ppm||Recommended packet size at ±100ppm|
|1(4-bits)||2 bits||2400 bytes||1200 bytes|
|2(8-bits)||6 bits||7200 bytes||3600 bytes|
|3(12-bits)||10 bits||12000 bytes||6000 bytes|
|0(16-bits)||14 bits||16800 bytes||8400 bytes|
The Serial Management Interface (SMI), provides access to the TLK111 internal register space for status information and configuration. The SMI is compatible with IEEE802.3-2002 clause 22. The implemented register set consists of all the registers required by the IEEE802.3-2002, plus several others to provide additional visibility and controllability of the TLK111 device.
The SMI includes the MDC management clock input and the management MDIO data pin. The MDC clock is sourced by the external management entity, also called Station (STA), and can run at a maximum clock rate of 25MHz. MDC is not expected to be continuous, and can be turned off by the external management entity when the bus is idle.
The MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is latched on the rising edge of the MDC clock. The MDIO pin requires a pull-up resistor (2.2kΩ) which, during IDLE and turnaround, pulls MDIO high.
Up to 32 PHYs can share a common SMI bus. To distinguish between the PHYs, a 5-bit address is used. During power-up reset, the TLK111 latches the PHYAD[4:0] configuration pins (Pin 42 to Pin 46) to determine its address.
The management entity must not start an SMI transaction in the first cycle after power-up reset. To maintain valid operation, the SMI bus must remain inactive at least one MDC cycle after hard reset is de-asserted.
In normal MDIO transactions, the register address is taken directly from the management-frame reg_addr field, thus allowing direct access to 32 16-bit registers (including those defined in IEEE802.3 and vendor specific). The data field is used for both reading and writing. The Start code is indicated by a <01> pattern. This pattern makes sure that the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no device may actively drive the MDIO signal during the first bit of Turnaround. The addressed TLK111 drives the MDIO with a zero for the second bit of turnaround and follows this with the required data. Figure 4-3 shows the timing relationship between MDC and the MDIO as driven/received by the Station (STA) and the TLK111 (PHY) for a typical register read access.
For write transactions, the station-management entity writes data to the addressed TLK111, thus eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity by inserting <10>. Figure 4-4 shows the timing relationship for a typical MII register write access. The frame structure and general read/write transactions are shown in Table 4-2, Figure 4-3, and Figure 4-4.
|MII Management Serial Protocol||<idle><start><op code><device addr><reg addr><turnaround><data><idle>|
|Read Operation||<idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>|
|Write Operation||<idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>|
The TLK111 SMI function supports read/write access to the extended register set using registers REGCR(0x000Dh) and ADDAR(0x000Eh) and the MDIO Manageable Device (MMD) indirect method defined in IEEE802.3ah Draft for clause 22 for accessing the clause 45 extended register set.
The standard register set, MDIO registers 0 to 31, is accessed using the normal direct-MDIO access or the indirect method, except for register REGCR(0x000Dh) and ADDAR(0x000Eh) which is accessed only using the normal MDIO transaction. The SMI function will ignore indirect accesses to these registers.
REGCR(0x000Dh) is the MDIO Manageable MMD access control. In general, register REGCR(4:0) is the device address DEVAD that directs any accesses of ADDAR(0x000Eh) register to the appropriate MMD. Specifically, the TLK111 uses the vendor-specific DEVAD[4:0] = "11111" for accesses. All accesses through registers REGCR and ADDAR must use this DEVAD. Transactions with other DEVAD are ignored. REGCR[15:14] holds the access function: address (00), data with no post increment (01), data with post increment on read and writes (10) and data with post increment on writes only (11).
The following sections describe how to perform operations on the extended register set using register REGCR and ADDAR.
To set the address register:
Subsequent writes to register ADDAR (step 2) continue to write the address register.
To read the address register:
Subsequent reads to register ADDAR (step 2) continue to read the address register.
To write a register in the extended register set:
Subsequent writes to register ADDAR (step 4) continue to rewrite the register selected by the value in the address register.
Note: steps (1) and (2) can be skipped if the address register was previously configured.
To read a register in the extended register set:
Subsequent reads from register ADDAR (step 4) continue reading the register selected by the value in the address register.
Note: steps (1) and (2) can be skipped if the address register was previously configured.
Subsequent writes to register ADDAR (step 4) write the next higher addressed data register selected by the value of the address register; the address register is incremented after each access.
To read a register in the extended register set and automatically increment the address register to the next higher value following the write operation:
Subsequent reads to register ADDAR (step 4) read the next higher addressed data register selected by the value of the address register; the address register is incremented after each access.