JAJSNP8A March   2023  – February 2024 TMAG6181-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Magnetic Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Magnetic Flux Direction
      2. 6.3.2 Sensors Location and Placement Tolerances
      3. 6.3.3 Magnetic Response
      4. 6.3.4 Parameters Definition
        1. 6.3.4.1 AMR Output Parameters
        2. 6.3.4.2 Transient Parameters
          1. 6.3.4.2.1 Power-On Time
        3. 6.3.4.3 Hall Sensor Parameters
        4. 6.3.4.4 Angle Accuracy Parameters
      5. 6.3.5 Automatic Gain Control (AGC)
      6. 6.3.6 Turns Counter
        1. 6.3.6.1 Rotation Tracking
      7. 6.3.7 Safety and Diagnostics
        1. 6.3.7.1 Device Level Checks
        2. 6.3.7.2 System Level Checks
    4. 6.4 Device Functional Modes
      1. 6.4.1 Operating Modes
        1. 6.4.1.1 Active Mode
        2. 6.4.1.2 Active-Turns Mode
        3. 6.4.1.3 Low-Power Mode
        4. 6.4.1.4 Sleep Mode
        5. 6.4.1.5 Fault Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Power Supply as the Reference for External ADC
      2. 7.1.2 AMR Output Dependence on Airgap Distance
      3. 7.1.3 Calibration of Sensor Errors
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Designing with Multiple Sensors
          1. 7.2.2.1.1 Designing for Redundancy
          2. 7.2.2.1.2 Multiplexing Multiple Sensors
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted); typical specifications are at TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AMR Output Parameters
Vout Single-ended output voltage peak to peak VCC = 3.3V 57 62 67.5 %VCC
Vout Single-ended output voltage peak to peak VCC = 5.5V 55 60 65 %VCC
k Amplitude asynchronism ratio (Vpk Cos/ Vpk Vsin) B  = 30mT, VCC = 3.3V –2.3 0.3 2.3 %
B  = 30mT, VCC = 5V –2.4 0.3 2.4 %
Voffset_room Differential offset of SIN/COS outputs at room  B = 30mT, TA = 25°C, VCC = 3.3V –56 56 mV
B = 30mT, TA = 25°C, VCC = 5V –90 90 mV
Voffset_tc Temperature coefficient of differential offset voltage B = 30mT,  VCC = 3.3V ±0.1 mV/°C
 
B = 30mT,  VCC = 5V ±0.1
mV/°C
VCM Common-mode output voltage B = 30mT,  VCC = 3.3V 48 50 52
%VCC
B = 30mT,  VCC = 5V 48 50 52
%VCC
VNOISE Output referred noise (differential) B = 30mT, Cload = 100pF 0.5 mVrms
Rout Series output resistance 55 Ω
Rout_sleep Series output resistance during Sleep SLEEP = GND 1 MΩ
tagc_update Update rate of the automatic gain control  After Vout reaching 60% of VCC 1 s
DC Power
VVCC_UV VCC undervoltage threshold 2.45 2.65 V
VVCC_OV VCC overvoltage threshold 5.9 6.36 V
VCCRAMP Power supply ramp rate for proper device start-up VCC = 10% to 90%
Specified by design		 0.2 ms
IACT Active mode current from VCC SLEEP = VCC  5 10 mA
IDCM_SLEEP Sleep mode current from VCC DCM mode enabled 50 µA
ISLEEP Sleep mode current from VCC SLEEP = GND 4.5 µA
ILP Average current during low power mode from VCC Low power DCM mode with turns counter enabled (no rotations detected) 50 µA
tsleep_no_rotation Sleep time during low power mode when the magnetic field is static (not rotating) B = 30 mT 25 ms
ton_startup Power-on time during start-up To achieve 90% of output voltages after VCC has reached final value (CLOAD =100pF) 38 85 µs
ton_sleep Power on time after SLEEP goes high  
To achieve 90% of output voltages after SLEEP > VIH (CLOAD =100pF) 
 		 45 50 µs
tsleep_pd Time that SLEEP must stay low when transitioning from active mode to low power mode 125 400 µs
tsleep_timeout Timeout between two consecutive pulses on SLEEP pin when entering low power mode 25 400 µs
tsleep_mode Time that SLEEP must stay low to enter sleep mode 1.1 ms
Digital I/O
VIH High level input voltage SLEEP 0.65 × VCC V
VIL Low level input voltage 0.3 × VCC V
VIH High level input voltage TURNS 0.65 × VCC V
VIL Low level input voltage 0.3 × VCC V
VOL Low level output voltage IO = 2mA on TURNS pin 0 0.4 V
Turns Counter
fPWM PWM carrier frequency When Turns Counter is enabled  2.5 KHz
DCPWM Output Valid Duty Cycle Range 10 90 %
TC Turns Counter Range –1024 1023
TCstep Turns Counter PWM Step Size 0.039 % / Turn
TC_PWMQ Quiescent Duty Cycle Turns Counter = 0 50 %
TC_PWMQΔL Quiescent Duty Cycle Lifetime drift  0.5 %
TCnoise RMS noise on PWM duty cycle of TURNS pin  0.005 %
Ttc_start Minimum Time required to pull down the TURNS pin to initiate the turns counter 125 µs
Ttc_reset Minimum Time required to pull down the TURNS pin to reset the turns counter 1.1 ms
Ttc_delay Time delay from rising edge on TURNS pin to the first PWM falling edge 55 µs