The TMP9R00-SP device has a two-wire interface
that is compatible with the I2C or SMBus interface. Figure 7-2 through Figure 7-7 illustrate the timing for various operations on the TMP9R00-SP
device. The bus definitions are as follows:
Bus Idle:Both SDA and SCL lines remain high.
Start Data Transfer:A change in the state of the SDA line (from high to low) when the SCL line is high defines a start condition. Each data transfer initiates with a start condition.
Stop Data Transfer:A change in the state of the SDA line (from low to high) when the SCL line is high defines a stop condition. Each data transfer terminates with a repeated start or stop condition.
Data Transfer:The number of data bytes transferred between a start and stop condition is not limited and is
determined by the controller device. The target acknowledges the data
transfer.
Acknowledge:Each receiving device, when addressed, is obliged to generate an acknowledge bit. A device that
acknowledges must pull down the SDA line during the acknowledge clock pulse
in such a way that the SDA line is stable low during the high period of the
acknowledge clock pulse. Take setup and hold times into account. On a
controller receive, data transfer termination can be signaled by the
controller generating a not-acknowledge on the last byte that is transmitted
by the target.
Figure 7-2 Two-Wire Timing Diagram for Write Pointer Byte
Figure 7-3 Two-Wire Timing Diagram for Write Pointer Byte and Value
Word
A. The controller
must leave SDA high to terminate a single-byte read
operation.
Figure 7-4 Two-Wire Timing Diagram for Pointer Set Followed by a Repeat
Start and Single-Byte Read Format
Figure 7-5 Two-Wire Timing Diagram for Pointer Byte Set Followed by a
Repeat Start and Word (Two-Byte) Read
Figure 7-6 Two-Wire Timing Diagram for Pointer Byte Set Followed by a
Repeat Start and Multiple-Word (N-Word) Read
Figure 7-7 Two-Wire Timing Diagram for Multiple-Word (N-Word) Read
Without a Pointer Byte Set