When reading from the TMP9R00-SP device, the last value stored in the pointer register by a write operation is used to determine which register is read by a read operation. To change which register is read for a read operation, a new value must be written to the pointer register. This transaction is accomplished by issuing a target address byte with the R/ W bit low, followed by the pointer register byte; no additional data are required. The controller can then generate a start condition and send the target address byte with the R/ W bit high to initiate the read command. See Figure 7-4 through Figure 7-6 for details of this sequence.

If repeated reads from the same register are desired, continually sending the pointer register bytes is not necessary because the TMP9R00-SP device retains the pointer register value until the value is changed by the next write operation. The register bytes are sent by the MSB first, followed by the LSB. If only one byte is read (MSB), a consecutive read of TMP9R00-SP device results in the MSB being transmitted first. The LSB can only be accessed through two-byte reads.

The controller terminates a read operation by issuing a not-acknowledge (NACK) command at the end of the last byte to be read or transmitting a stop condition. For a single-byte operation, the controller must leave the SDA line high during the acknowledge time of the first byte that is read from the target

The TMP9R00-SP register structure has a word (two-byte) length, so every write transaction must have an even number of bytes (MSB and LSB) following the pointer register value (see Figure 7-3). Data transfers occur during the ACK at the end of the second byte or LSB. If the transaction does not finish, signaled by the ACK at the end of the second byte, then the data is ignored and not loaded into the TMP9R00-SP register. Read transactions do not have the same restrictions and may be terminated at the end of the last MSB.