JAJSO44 june   2023 TMUX582F-SEP

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics (Global)
    6. 6.6 Dual Supply: Electrical Characteristics
    7. 6.7 Single Supply: Electrical Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  Input and Output Leakage Current Under Overvoltage Fault
    5. 7.5  Break-Before-Make Delay
    6. 7.6  Enable Delay Time
    7. 7.7  Transition Time
    8. 7.8  Fault Response Time
    9. 7.9  Fault Recovery Time
    10. 7.10 Fault Flag Response Time
    11. 7.11 Fault Flag Recovery Time
    12. 7.12 Charge Injection
    13. 7.13 Off Isolation
    14. 7.14 Crosstalk
    15. 7.15 Bandwidth
    16. 7.16 THD + Noise
  9. 8 Truth Table
  10. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1 Flat ON- Resistance
      2. 9.2.2 Protection Features
        1. 9.2.2.1 Input Voltage Tolerance
        2. 9.2.2.2 Powered-Off Protection
        3. 9.2.2.3 Fail-Safe Logic
        4. 9.2.2.4 Overvoltage Protection and Detection
        5. 9.2.2.5 Adjacent Channel Operation During Fault
        6. 9.2.2.6 ESD Protection
        7. 9.2.2.7 Latch-Up Immunity
        8. 9.2.2.8 EMC Protection
      3. 9.2.3 Overvoltage Fault Flags
      4. 9.2.4 Bidirectional and Rail-to-Rail Operation
      5. 9.2.5 1.8 V Logic Compatible Inputs
      6. 9.2.6 Integrated Pull-Down Resistor on Logic Pins
    3. 9.3 Device Functional Modes
      1. 9.3.1 Normal Mode
      2. 9.3.2 Fault Mode
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 System Diagnostics – Telemetry
      2. 10.2.2 Design Requirements
      3. 10.2.3 Detailed Design Procedure
      4. 10.2.4 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  15. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Tape and Reel Information
    2. 14.2 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.7 Latch-Up Immunity

Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the low impedance path.

The TMUX582F-SEP devices are constructed on silicon on insulator (SOI) based process where an oxide layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events due to overvoltage or current injections. The latch-up immunity feature allows the TMUX582F-SEP to be used in harsh environments. For more information on latch-up immunity, refer to Using Latch Up Immune Multiplexers to Help Improve System Reliability.