SLOS367E August   2003  – November 2015 TPA6211A1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operation Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Operating Characteristics
    7. 7.7 Dissipation Ratings
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fully Differential Amplifier Efficiency and Thermal Information
        1. 9.3.1.1 Advantages of Fully Differential Amplifiers
        2. 9.3.1.2 Differential Output Versus Single-Ended Output
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Selecting Components
          1. 10.2.2.1.1 Resistors (RI)
          2. 10.2.2.1.2 Bypass Capacitor (CBYPASS) and Start-Up Time
          3. 10.2.2.1.3 Input Capacitor (CI)
          4. 10.2.2.1.4 Band-Pass Filter (Ra, Ca, and Ca)
            1. 10.2.2.1.4.1 Step 1: Low-Pass Filter
            2. 10.2.2.1.4.2 Step 2: High-Pass Filter
            3. 10.2.2.1.4.3 Step 3: Additional Low-Pass Filter
          5. 10.2.2.1.5 Decoupling Capacitor (CS)
          6. 10.2.2.1.6 Using Low-ESR Capacitors
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Decoupling Capacitor
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DGN|8
  • DRB|8
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range unless otherwise noted(1)
MIN MAX UNIT
VDD Supply voltage –0.3 6 V
VI Input voltage –0.3 VDD + 0.3 V
Continuous total power dissipation See Dissipation Ratings
TA Operating free-air temperature –40 85 °C
TJ Junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operation Conditions

MIN NOM MAX UNIT
VDD Supply voltage 2.5 5.5 V
VIH High-level input voltage SHUTDOWN 1.55 V
VIL Low-level input voltage SHUTDOWN 0.5 V
TA Operating free-air temperature –40 85 °C

7.4 Thermal Information

THERMAL METRIC(1) TPA6211A1 UNIT
DGN (MSOP-PowerPAD™) DRB (SON)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 62.8 49.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 61.9 24.8 °C/W
RθJB Junction-to-board thermal resistance 42.1 58.8 °C/W
ψJT Junction-to-top characterization parameter 3.3 1.7 °C/W
ψJB Junction-to-board characterization parameter 41.9 25 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 11 8.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOS Output offset voltage (measured
differentially)		 VI = 0 V differential, Gain = 1 V/V, VDD = 5.5 V -9 0.3 9 mV
PSRR Power supply rejection ratio VDD = 2.5 V to 5.5 V –85 –60 dB
VIC Common mode input range VDD = 2.5 V to 5.5 V 0.5 VDD-0.8 V
CMRR Common mode rejection ratio VDD = 5.5 V, VIC = 0.5 V to 4.7 V -63 –40 dB
VDD = 2.5 V, VIC = 0.5 V to 1.7 V -63 –40
Low-output swing RL = 4 Ω,
VIN+ = VDD,
VIN+ = 0 V,		 Gain = 1 V/V,
VIN- = 0 V or
VIN- = VDD		 VDD = 5.5 V 0.45 V
VDD = 3.6 V 0.37
VDD = 2.5 V 0.26 0.4
High-output swing RL = 4 Ω,
VIN+ = VDD,
VIN- = VDD		 Gain = 1 V/V,
VIN- = 0 V or
VIN+ = 0 V		 VDD = 5.5 V 4.95 V
VDD = 3.6 V 3.18
VDD = 2.5 V 2 2.13
| IIH | High-level input current, shutdown VDD = 5.5 V, VI = 5.8 V 58 100 μA
| IIL | Low-level input current, shutdown VDD = 5.5 V, VI = –0.3 V 3 100 μA
IQ Quiescent current VDD = 2.5 V to 5.5 V, no load 4 5 mA
I(SD) Supply current V(SHUTDOWN) ≤ 0.5 V, VDD = 2.5 V to 5.5 V,
RL = 4Ω 		0.01 1 μA
Gain RL = 4Ω TPA6211A1 q_tblmin_los367.gif TPA6211A1 q_tbltyp_los367.gif TPA6211A1 q_tblmax_los367.gif V/V
Resistance from shutdown to GND 100 kΩ

7.6 Operating Characteristics

TA = 25°C, Gain = 1 V/V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PO Output power THD + N= 1%, f = 1 kHz, RL = 3 Ω VDD = 5 V 2.45 W
VDD = 3.6 V 1.22
VDD = 2.5 V 0.49
THD + N= 1%, f = 1 kHz, RL = 4 Ω VDD = 5 V 2.22
VDD = 3.6 V 1.1
VDD = 2.5 V 0.47
THD + N= 1%, f = 1 kHz, RL = 8 Ω VDD = 5 V 1.36
VDD = 3.6 V 0.72
VDD = 2.5 V 0.33
THD+N Total harmonic distortion plus noise f = 1 kHz, RL = 3 Ω PO = 2 W VDD = 5 V 0.045%
PO = 1 W VDD = 3.6 V 0.05%
PO = 300 mW VDD = 2.5 V 0.06%
f = 1 kHz, RL = 4 Ω PO = 1.8 W VDD = 5 V 0.03%
PO = 0.7 W VDD = 3.6 V 0.03%
PO = 300 mW VDD = 2.5 V 0.04%
f = 1 kHz, RL = 8 Ω PO = 1 W VDD = 5 V 0.02%
PO = 0.5 W VDD = 3.6 V 0.02%
PO = 200 mW VDD = 2.5 V 0.03%
kSVR Supply ripple rejection ratio VDD = 3.6 V, Inputs ac-grounded with
Ci = 2 μF, V(RIPPLE) = 200 mVpp		 f = 217 Hz -80 dB
f = 20 Hz to 20 kHz -70
SNR Signal-to-noise ratio VDD = 5 V, PO = 2 W, RL = 4 Ω 105 dB
Vn Output voltage noise VDD = 3.6 V, f = 20 Hz to 20 kHz,
Inputs ac-grounded with Ci = 2 μF		 No weighting 15 μVRMS
A weighting 12
CMRR Common mode rejection ratio VDD = 3.6 V, VIC = 1 Vpp f = 217 Hz -65 dB
ZI Input impedance 38 40 44 kΩ
Start-up time from shutdown VDD = 3.6 V, No CBYPASS 4 μs
VDD = 3.6 V, CBYPASS = 0.1 μF 27 ms

7.7 Dissipation Ratings

PACKAGE TA ≤ 25°C
POWER RATING		 DERATING
FACTOR(1)		 TA= 70°C
POWER RATING		 TA= 85°C
POWER RATING
DGN 2.13 W 17.1 mW/°C 1.36 W 1.11 W
DRB 2.7 W 21.8 mW/°C 1.7 W 1.4 W
(1) Derating factor based on high-k board layout.

7.8 Typical Characteristics

Table 1. Table of Graphs

FIGURE
PO Output power vs Supply voltage Figure 1
vs Load resistance Figure 2
PD Power dissipation vs Output power Figure 3, Figure 4
THD+N Total harmonic distortion + noise vs Output power Figure 5, Figure 6, Figure 7
vs Frequency Figure 8, Figure 9, Figure 10, Figure 11, , Figure 12
vs Common-mode input voltage Figure 13
KSVR Supply voltage rejection ratio vs Frequency Figure 14, Figure 15, Figure 16, Figure 17
KSVR Supply voltage rejection ratio vs Common-mode input voltage Figure 18
GSM Power supply rejection vs Time Figure 19
GSM Power supply rejection vs Frequency Figure 20
CMRR Common-mode rejection ratio vs Frequency Figure 21
vs Common-mode input voltage Figure 22
Closed loop gain/phase vs Frequency Figure 23
Open loop gain/phase vs Frequency Figure 24
IDD Supply current vs Supply voltage Figure 25
vs Shutdown voltage Figure 26
Start-up time vs Bypass capacitor Figure 27
TPA6211A1 tc_out_psv_los367.gif
Figure 1. Output Power vs Supply Voltage
TPA6211A1 tc_powerd_los367.gif
Figure 3. Power Dissipation vs Output Power
TPA6211A1 tc_totalh_los367.gif
Figure 5. Total Harmonic Distortion + Noise vs Output Power
TPA6211A1 tc_totalh2_los367.gif
Figure 7. Total Harmonic Distortion + Noise vs Output Power
TPA6211A1 tc_totalhf1_los367.gif
Figure 9. Total Harmonic Distortion + Noise vs Frequency
TPA6211A1 tc_totalhf3_los367.gif
Figure 11. Total Harmonic Distortion + Noise vs Frequency
TPA6211A1 tc_totharm_los367.gif
Figure 13. Total Harmonic Distortion + Noise vs Common Mode Input Voltage
TPA6211A1 tc_supvol1_los367.gif
Figure 15. Supply Voltage Rejection Ratio vs Frequency
TPA6211A1 tc_supvol3_los367.gif
Figure 17. Supply Voltage Rejection Ratio vs Frequency
TPA6211A1 tc_GSM_los367.gif
Figure 19. GSM Power Supply Rejection vs Time
TPA6211A1 tc_CMRR_los367.gif
Figure 21. Common Mode Rejection Ratio vs Frequency
TPA6211A1 tc_closedl_los367.gif
Figure 23. Closed Loop Gain/Phase vs Frequency
TPA6211A1 tc_supcurr_los367.gif
Figure 25. Supply Current vs Supply Voltage
TPA6211A1 tc_startup_los367.gif
Figure 27. Start-Up Time vs Bypass Capacitor
TPA6211A1 tc_out_plr_los367.gif
Figure 2. Output Power vs Load Resistance
TPA6211A1 tc_powerd1_los367.gif
Figure 4. Power Dissipation vs Output Power
TPA6211A1 tc_totalh1_los367.gif
Figure 6. Total Harmonic Distortion + Noise vs Output Power
TPA6211A1 tc_totalhf_los367.gif
Figure 8. Total Harmonic Distortion + Noise vs Frequency
TPA6211A1 tc_totalhf2_los367.gif
Figure 10. Total Harmonic Distortion + Noise vs Frequency
TPA6211A1 tc_totalhf4_los367.gif
Figure 12. Total Harmonic Distortion + Noise vs Frequency
TPA6211A1 tc_supvol_los367.gif
Figure 14. Supply Voltage Rejection Ratio vs Frequency
TPA6211A1 tc_supvol2_los367.gif
Figure 16. Supply Ripple Rejection Ratio vs Frequency
TPA6211A1 tc_supplyDC_los367.gif
Figure 18. Supply Voltage Rejection Ratio vs DC Common Mode Input
TPA6211A1 tc_GSM1_los367.gif
Figure 20. GSM Power Supply Rejection vs Frequency
TPA6211A1 tc_CMMR1_los367.gif
Figure 22. Common-Mode Rejection Ratio vs Common-Mode Input Voltage
TPA6211A1 tc_openl_los367.gif
Figure 24. Open Loop Gain/Phase vs Frequency
TPA6211A1 tc_supcurr1_los367.gif
Figure 26. Supply Current vs Shutdown Voltage