SLVSCK3C May   2014  – February 2017 TPD4E6B06

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 IEC 61000-4-2 Level 2 ESD Protection
      2. 7.3.2 IEC 61000-4-5 Surge Protection
      3. 7.3.3 IO Capacitance
      4. 7.3.4 RDYN
      5. 7.3.5 DC Breakdown Voltage
      6. 7.3.6 Ultra-Low Leakage Current
      7. 7.3.7 Clamping Voltage
      8. 7.3.8 Industrial Temperature Range
      9. 7.3.9 Space Saving DPW Package
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Detailed Description

7.1 Overview

The TPD4E6B06 is a four channel ESD Protection device in an ultra small DPW package. It is the industry’s smallest 4-CH ESD protection device with 0.48-mm pitch. This larger pitch helps save on PCB manufacturing costs. The device provides IEC61000-4-2 compliance up to 15-kV contact discharge. It has an ESD clamp circuit with back-to-back diodes for bipolar/bidirectional signal support. The 4.8-pF (Typical) line capacitance is suitable for a wide range of applications supporting frequencies up to 700 MHz.

7.2 Functional Block Diagram

TPD4E6B06 fbd_slvsck3.gif

7.3 Feature Description

7.3.1 IEC 61000-4-2 Level 2 ESD Protection

The IO pins can withstand ESD events up to ±15-kV contact and ±15-kV air. An ESD-surge clamp diverts the current to ground.

7.3.2 IEC 61000-4-5 Surge Protection

The IO pins can withstand surge events up to 3 A and 40 W (8/20 µs waveform). An ESD-surge clamp diverts this current to ground.

7.3.3 IO Capacitance

The capacitance between any IO pin to ground is 4.8 pF (typical). This capacitance supports frequencies up to 700 MHz.

7.3.4 RDYN

The low RDYN of 0.75 Ω (typical) allows for lower clamping voltages.

7.3.5 DC Breakdown Voltage

The DC breakdown voltage of any IO pin is a minimum of ±6 V. This ensures that sensitive equipment is protected from surges above the reverse standoff voltage of ±5.5 V (minimum).

7.3.6 Ultra-Low Leakage Current

The IO pins feature an ultra-low leakage current of 100 nA (maximum) with a bias of 2.5 V.

7.3.7 Clamping Voltage

The IO pins feature an ESD clamp capable of clamping the voltage to 10 V (IO to GND) or 9 V (GND to IO) of IEC61000-4-5 surge when IPP = 1 A.

7.3.8 Industrial Temperature Range

This device features an industrial operating range of –40°C to +125°C.

7.3.9 Space Saving DPW Package

The small 0.8 mm × 0.8 mm package size saves board space and makes it easy to add ESD protection.

7.4 Device Functional Modes

The TPD4E6B06 is a passive integrated circuit that triggers when voltages are above VBRF or VBRR. During ESD events, voltages as high as ±15 kV (air) can be directed to ground via the internal diode network. Once the voltages on the protected line fall below the trigger levels of the TPD4E6B06 (usually within 10s of nano-seconds) the device reverts to passive.