SLVSCT5D March   2015  – September 2016 TPS22953 , TPS22954

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics—VBIAS = 5 V
    7. 7.7  Electrical Characteristics—VBIAS = 3.3 V
    8. 7.8  Electrical Characteristics—VBIAS = 2.5 V
    9. 7.9  Switching Characteristics—CT = 1000 pF
    10. 7.10 Switching Characteristics—CT = 0 pF
    11. 7.11 Typical DC Characteristics
    12. 7.12 Typical Switching Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  On and Off Control (EN pin)
      2. 9.3.2  Voltage Monitoring (SNS Pin)
      3. 9.3.3  Power Good (PG Pin)
      4. 9.3.4  Supervisor Fault Detection and Automatic Restart
      5. 9.3.5  Manual Restart
      6. 9.3.6  Thermal Shutdown
      7. 9.3.7  Reverse Current Blocking (TPS22953 Only)
      8. 9.3.8  Quick Output Discharge (QOD) (TPS22954 Only)
      9. 9.3.9  VIN and VBIAS Voltage Range
      10. 9.3.10 Adjustable Rise Time (CT pin)
      11. 9.3.11 Power Sequencing
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Input to Output Voltage Drop
      2. 10.1.2 Thermal Considerations
      3. 10.1.3 Automatic Power Sequencing
      4. 10.1.4 Monitoring a Downstream Voltage
      5. 10.1.5 Monitoring the Input Voltage
      6. 10.1.6 Break-Before-Make Power MUX (TPS22953 Only)
      7. 10.1.7 Make-Before-Break Power MUX (TPS22953 Only)
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inrush Current
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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発注情報

9 Detailed Description

9.1 Overview

The TPS22953/4 are 5.7-V, 5-A load switches in 10-pin SON packages. To reduce voltage drop for low voltage, high current rails the device implements a low resistance N-channel MOSFET, which reduces the drop out voltage through the device at high currents. The integrated adjustable undervoltage lockout (UVLO) and adjustable power good (PG) threshold provides voltage monitoring as well as robust power sequencing.

The adjustable rise time control of the device greatly reduces inrush current for a wide variety of bulk load capacitances, thereby reducing or eliminating power supply droop. The switch is independently controlled by an on and off input (EN), which is capable of interfacing directly with low-voltage control signals. A 15-Ω on-chip load resistor is integrated into the device for output quick discharge when switch is turned off.

During shutdown, the device has very low leakage currents, thereby reducing unneccessary leakages for downstream modules during standby. Integrated power monitoring functionality, control logic, driver, power supply, and output discharge FET eliminates the need for any external components, which reduces solution size and BOM count.

9.2 Functional Block Diagram

TPS22954 TPS22953 Block_Diagram.gif

9.3 Feature Description

9.3.1 On and Off Control (EN pin)

The EN pin controls the state of the switch. When the voltage on EN has exceeded VIH,EN the switch is enabled. When EN goes below VIL,EN the switch is disabled.

The EN pin has a blanking time of tBLANK on the rising edge once the VIH,EN threshold has been exceeded. It also has a de-glitch time of tDEGLITCH when the voltage has gone below VIL,EN.

The EN pin can also be configured via an external resistor divider to monitor a voltage signal for input UVLO. See Equation 1 and Figure 53 on how to configure the EN pin for input UVLO.

Equation 1. TPS22954 TPS22953 Eq01_vihen_slvsct5.gif

where

  • VIH,EN is the rising threshold of the EN pin (see the Electrical Characteristics table)
  • VIN is the input voltage being monitored (this could be VIN, VBIAS, or an external power supply)
  • REN1, REN2 is the resistor divider values
TPS22954 TPS22953 VEN.gif Figure 53. Resistor Divider (EN Pin)

9.3.2 Voltage Monitoring (SNS Pin)

The SNS pin of the device can be used to monitor the output voltage of the device or another voltage rail. The pin can be configured with an external resistor divider to set the desired trip point for the voltage being monitored or be tied to OUT directly. If the voltage on the SNS pin exceeds VIH,SNS, the voltage being monitored on the SNS pin is considered to be valid high. The voltage on the SNS pin must be greater than VIH,SNS for at least tBLANK before PG is asserted high. If the voltage on the SNS pin goes below VIL,SNS, then the switch powers cycle (i.e., the switch is disabled and re-enabled). For proper functionality of the device, this pin must not be left floating. If a resistor divider is not being used for voltage sensing, this pin can be tied directly to VOUT.

The SNS pin has a blanking time of tBLANK on the rising edge once the VIH,SNS threshold has been exceeded. It has a de-glitch time of tDEGLITCH when the voltage has gone below VIL,SNS.

See Equation 2 and Figure 54 on how to configure the SNS pin for voltage monitoring.

Equation 2. TPS22954 TPS22953 Eq02_vihsns_slvsct5.gif

where

  • VIH,SNS is the the rising threshold of the SNS pin (see Electrical Characteristics table)
  • VOUT is the voltage on the OUTpin
  • RSNS1, RSNS2 is the resistor divider values
TPS22954 TPS22953 VSNS.gif Figure 54. Voltage Divdier (SNS Pin)

9.3.3 Power Good (PG Pin)

The PG pin is only asserted high when the voltage on EN has exceeded VIH,EN and the voltage on SNS has exceeded VIH,SNS. There is a tBLANK time, typically 100 µs, between the SNS voltage exceeding VIH,SNS and PG being asserted high. If the voltage on EN goes below VIL,EN or the voltage on SNS goes below VIL,SNS, PG is de-asserted. There is a tDEGLITCH time, typically 5µs, between the EN voltage or SNS voltage going below their respective VIL levels and PG being pulled low.

PG is an open drain pin and must be pulled up with a pull-up resistor. Be sure to never exceed the maximum operating voltage on this pin. If PG is not being used in the application, tie it to GND for proper device functionality.

For proper PG operation, the BIAS voltage must be within the recommended operating range. In systems that are very sensitive to noise or have long PG traces, it is recommended to add a small capacitance from PG to GND for decoupling.

9.3.4 Supervisor Fault Detection and Automatic Restart

The falling edge of the SNS pin below VIL,SNS is considered a fault case and causes the load switch to be disabled for tRESTART (typically 2 ms). After the tRESTART time, the switch is automatically re-enabled as long as EN is still above VIH,EN . In the case the SNS pin is being used to monitor VOUT or a downstream voltage, the restart helps to protect against excessive over-current if there is a quick short to GND. See Figure 55.

TPS22954 TPS22953 tRESTART.gif Figure 55. Automatic Restart after Quick Short to GND

9.3.5 Manual Restart

The falling edge of the SNS pin below VIL,SNS is considered a fault case and causes the load switch to be disabled for tRESTART (typically 2 ms). The SNS pin can be driven by an MCU to manually reset the load switch. After the tRESTART time, the switch is automatically re-enabled as long as EN is still above VIH,EN , even is SNS is held low. The PG pin stays low until the switch is re-enabled and the SNS pin rises above VIH,SNS. See Figure 56.

TPS22954 TPS22953 tRESTART_man.gif Figure 56. Manual Restart (SNS Held Low)

If the SNS pin is brought above VIH,SNS within the tRESTART time, the switch still waits to re-enable. The PG pin also stays low until tBLANK after switch is re-enabled. In this case, PG indicates when the switch is enabled and capable of being reset again. See Figure 57.

TPS22954 TPS22953 tRESTART_man_high.gif Figure 57. Manual Restart (SNS Toggled Low to High)

9.3.6 Thermal Shutdown

If the junction temperature of the device exceeds TSD, the switch is disabled. The device is enabled once the junction temperature drops by TSDHYS as long as EN is still greater than VIH,EN.

9.3.7 Reverse Current Blocking (TPS22953 Only)

When the switch is disabled (either by de-asserting EN or SNS, triggering thermal shutdown, or losing power), the reverse current blocking (RCB) feature of the device is engaged within tRCB, typically 10 μs. Once the RCB is engaged, the reverse current from the OUT pin to the IN pin is limited to IRCB,IN, typically 0.01 μA.

9.3.8 Quick Output Discharge (QOD) (TPS22954 Only)

The quick output discharge (QOD) transistor is engaged indefinitely whenever the switch is disabled and the recommended VBIAS voltage is met. During this state, the QOD resistance (RPD) discharges VOUT to GND. It is not recommended to apply a continuous DC voltage to OUT when the device is disabled.

The QOD transistor can remain active for a short period of time even after VBIAS loses power. This brief period of time is defined as tDIS. For best results, it is recommended the device get disabled before VBIAS goes below the minimum recommended voltage. The waveform in Figure 58 shows the behaviour when power is applied and then removed in a typical application.

TPS22954 TPS22953 tdis.gif Figure 58. Power Applied and then Removed in a Typical Application

At the end of the tDIS time, it is not guaranteed that VOUT will be 0 V since the final voltage is dependent upon the initial voltage and the CL capacitor. The final VOUT can be calculated with Equation 3 for a given initial voltage and CL capacitor.

Equation 3. TPS22954 TPS22953 Eq03_Vf_slvsct5.gif

where

  • Vf is the final VOUT voltage
  • Vo is the initial VOUT voltage
  • R is the the value of the output discharge resistor, RPD (see the Electrical Characteristics table)
  • C is the output bulk capacitance on OUT

9.3.9 VIN and VBIAS Voltage Range

For optimal RON performance, make sure VIN ≤ VBIAS. The device is still functional if VIN > VBIAS but it exhibits RON greater than what is listed in the Electrical Characteristics table. See Figure 59 for an example of a typical device. Notice the increasing RON as VIN increases. Be sure to never exceed the maximum voltage rating for VIN and VBIAS.

TPS22954 TPS22953 D031_SLVSCT5A.gif Figure 59. RON When VIN > VBIAS

9.3.10 Adjustable Rise Time (CT pin)

A capacitor to GND on the CT pin sets the slew rate for VOUT. An appropriate capacitance value must be placed on CT such that the IMAX and IPLS specifications of the device are not violated. The capacitor to GND on the CT pin must be rated for 25 V or higher. An approximate formula for the relationship between CT (except for CT = open) and the slew rate for any VBIAS is shown in Equation 4.

Equation 4. SR = 0.35 × CT + 20

where

  • SR is the slew rate (in μs/V)
  • CT is the the capacitance value on the CT terminal (in pF)
  • The units for the constant 20 are μs/V.
  • The units for the constant 0.35 are μs/(V*pF).

Rise time can be calculated by multiplying the input voltage (typically 10% to 90%) by the slew rate. Table 1 contains rise time values measured on a typical device.

Table 1. Rise Time

CTx (pF) RISE TIME (µs) 10%–90%, CL = 0.1 µF, VBIAS = 2.5 V to 5.7 V, RL=10 Ω LOAD.
TYPICAL VALUES AT 25°C, 25 V X7R 10% CERAMIC CAP
5 V 3.3 V 1.8 V 1.5 V 1.2 V 0.7 V
Open 140 98 62 54 46 32
220 444 301 175 150 124 81
470 767 518 299 255 210 133
1000 1492 994 562 474 387 245
2200 3105 2050 1151 961 787 490
4700 6420 4246 2365 1980 1612 998
10000 14059 9339 5183 4331 3533 2197

9.3.11 Power Sequencing

The TPS2295x operates regardless of power-on and power-off sequencing order. The order in which voltages are applied to IN, BIAS, and EN will not damage the device as long as the voltages do not exceed the absolute maximum operating conditions. If voltage is applied to EN before IN and BIAS, the slew rate of VOUT will not be controlled. Also, turning off IN and/or BIAS while EN is high will not damage the device.

9.4 Device Functional Modes

Table 2 describes what the OUT pin is connected to for a particular device as determined by the EN pin.

Table 2. Function Table

EN TPS22953 TPS22954
L OPEN RPD to GND
H IN IN