JAJSJE8A May   2021  – March 2022 TPS25830A-Q1 , TPS25832A-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Buck Regulator
      2. 10.3.2  Enable/UVLO and Start-Up
      3. 10.3.3  Switching Frequency and Synchronization (RT/SYNC)
      4. 10.3.4  Spread-Spectrum Operation
      5. 10.3.5  VCC, VCC_UVLO
      6. 10.3.6  Minimum ON-Time, Minimum OFF-Time
      7. 10.3.7  Internal Compensation
      8. 10.3.8  Bootstrap Voltage (BOOT)
      9. 10.3.9  RSNS, RSET, RILIMIT and RIMON
      10. 10.3.10 Overcurrent and Short Circuit Protection
        1. 10.3.10.1 Current Limit Setting using RILIMIT
        2. 10.3.10.2 Current Limit Setting for MFI OCP
        3. 10.3.10.3 Buck Average Current Limit Design Example
        4. 10.3.10.4 External MOSFET Gate Drivers
        5. 10.3.10.5 Cycle-by-Cycle Buck Current Limit
      11. 10.3.11 Overvoltage, IEC and Short to Battery Protection
        1. 10.3.11.1 VBUS and VCSN/OUT Overvoltage Protection
        2. 10.3.11.2 DP_IN and DM_IN Protection
        3. 10.3.11.3 CC IEC and OVP Protection
      12. 10.3.12 Cable Compensation
        1. 10.3.12.1 Cable Compensation Design Example
      13. 10.3.13 USB Port Control
      14. 10.3.14 FAULT Response
      15. 10.3.15 USB Specification Overview
      16. 10.3.16 USB Type-C® Basics
        1. 10.3.16.1 Configuration Channel
        2. 10.3.16.2 Detecting a Connection
        3. 10.3.16.3 Configuration Channel Pins CC1 and CC2
        4. 10.3.16.4 Current Capability Advertisement and VCONN Overload Protection
        5. 10.3.16.5 Plug Polarity Detection
      17. 10.3.17 Device Power Pins (IN, CSN/OUT, and PGND)
      18. 10.3.18 Thermal Shutdown
      19. 10.3.19 Power Wake
    4. 10.4 Device Functional Modes
      1. 10.4.1 Shutdown Mode
      2. 10.4.2 Standby Mode
      3. 10.4.3 Active Mode
      4. 10.4.4 Device Truth Table (TT)
      5. 10.4.5 USB Port Operating Modes
        1. 10.4.5.1 USB Type-C® Mode
        2. 10.4.5.2 Standard Downstream Port (SDP) Mode — USB 2.0, USB 3.0, and USB 3.1
        3. 10.4.5.3 Charging Downstream Port (CDP) Mode
        4. 10.4.5.4 Client Mode
      6. 10.4.6 High-Bandwidth Data-Line Switches
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1  Output Voltage
        2. 11.2.2.2  Switching Frequency
        3. 11.2.2.3  Inductor Selection
        4. 11.2.2.4  Output Capacitor Selection
        5. 11.2.2.5  Input Capacitor Selection
        6. 11.2.2.6  Bootstrap Capacitor Selection
        7. 11.2.2.7  VCC Capacitor Selection
        8. 11.2.2.8  Enable and Undervoltage Lockout Set-Point
        9. 11.2.2.9  Current Limit Set-Point
        10. 11.2.2.10 Cable Compensation Set-Point
        11. 11.2.2.11 LD_DET, POL, and FAULT Resistor Selection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Ground Plane and Thermal Considerations
    3. 13.3 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Related Links
    3. 14.3 ドキュメントの更新通知を受け取る方法
    4. 14.4 サポート・リソース
    5. 14.5 Trademarks
    6. 14.6 静電気放電に関する注意事項
    7. 14.7 用語集
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.3.3 Switching Frequency and Synchronization (RT/SYNC)

The switching frequency of the TPS2583xA-Q1 can be programmed by the resistor RT from the RT/SYNC pin and GND pin. To determine the RT resistance, for a given switching frequency, use Equation 3:

Equation 3. GUID-20210518-CA0I-ZVHN-ZJRF-7678SMVPPGLF-low.gif
GUID-75587DEF-D1E5-4545-BDF8-A41F75298EAC-low.gifFigure 10-6 RT Set Resistor vs Switching Frequency

Table 10-1 lists typical RT resistors values.

Table 10-1 Setting the Switching Frequency with RT
RT (kΩ)SWITCHING FREQUENCY (kHz)
68.1300
49.9400
39.2500
19.11000
12.41500
9.092000
8.662100
8.252200

TPS2583xA-Q1 switching action can be synchronized to an external clock from 300 kHz to 2.3 MHz.
The RT/SYNC pin can be used to synchronize the internal oscillator to an external clock. The internal oscillator can be synchronized by AC coupling a positive edge into the RT/SYNC pin. The AC coupled peak-to-peak voltage at the RT/SYNC pin must exceed the SYNC amplitude threshold of 2.0 V (minimum) to trip the internal synchronization pulse detector, and the minimum SYNC clock ON and OFF time must be longer than 100 ns (typical). When using a low impedance signal source, the frequency setting resistor RT is connected in parallel with an AC coupling capacitor CCOUP to a termination resistor RTERM (for example, 50 Ω). The two resistors in series provide the default frequency setting resistance when the signal source is turned off. A 10-pF ceramic capacitor can be used for CCOUP. Figure 10-7 shows the device synchronized to an external clock.

GUID-2EA5BEB5-DE15-4570-AE37-CE131F7974C4-low.gifFigure 10-7 Synchronize to External Clock

In order to avoid AM radio frequency band and maintain proper regulation when minimum ON-time or minimum OFF-time is reached, the TPS2583xA-Q1 implements a frequency foldback scheme depending on VIN voltage, refer to Figure 8-11.

  • When 8 V < VIN ≤ 19 V, the switching frequency of TPS2583xA-Q1 is determined by RT resistor or external sync clock.
  • When VIN ≤ 8 V, the switching frequency of TPS2583xA-Q1 is set to default 420 kHz, regardless of RT resistor setting or external sync clock.
  • When VIN > 19 V, the switching frequency of TPS2583xA-Q1 is set to default 420 kHz, regardless of RT resistor setting or external sync clock.

Figure 10-8, Figure 10-9 and Figure 10-10 show the device switching frequency and behavior under different VIN voltage and RT = 8.66 kΩ.

Figure 10-11, Figure 10-12 and Figure 10-13 show the device switching frequency and behavior under different VIN voltage and synchronized to an external 2.1-M system clock.

GUID-20210504-CA0I-CWVV-WRKZ-ZGHJ0HCWX596-low.gif
VIN = 7.5 V L = 3.3 uH ILOAD = 3 A
Figure 10-8 Switching Frequency When RT = 8.66 kΩ
GUID-20210504-CA0I-LRHF-2LXB-6BN8FF6F0HCD-low.gif
VIN = 20 V L = 3.3 uH ILOAD = 3 A
Figure 10-10 Switching Frequency When RT = 8.66 kΩ
GUID-20210504-CA0I-XPXK-LJ79-WZQBMW68CJ6F-low.gif
VIN = 13.5 V L = 3.3 uH ILOAD = 3 A
Figure 10-12 Synchronizing to External 2.1-MHz Clock
GUID-20210504-CA0I-5B8X-ZZMC-9W59VGTW6BFC-low.gif
VIN = 13.5 V L = 3.3 uH ILOAD = 3 A
Figure 10-9 Switching Frequency When RT = 8.66 kΩ
GUID-20210504-CA0I-VM7G-L5HX-LPRZF5LCMHPT-low.gif
VIN = 7.5 V L = 3.3 uH ILOAD = 3 A
Figure 10-11 Synchronizing to External 2.1-MHz Clock
GUID-20210504-CA0I-VM8M-8PBR-PSX9G6L8PWCD-low.gif
VIN = 20 V L = 3.3 uH ILOAD = 3 A
Figure 10-13 Synchronizing to External 2.1-MHz Clock