JAJSHQ8D July   2019  – July 2021 TPS25832-Q1 , TPS25833-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
    1.     18
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Buck Regulator
      2. 10.3.2  Enable/UVLO and Start-up
      3. 10.3.3  RT/SYNC
      4. 10.3.4  Spread-Spectrum Operation
      5. 10.3.5  VCC, VCC_UVLO
      6. 10.3.6  Minimum ON-time, Minimum OFF-time
      7. 10.3.7  Internal Compensation
      8. 10.3.8  Bootstrap Voltage (BOOT)
      9. 10.3.9  RSNS, RSET, RILIMIT, and RIMON
      10. 10.3.10 Overcurrent and Short Circuit Protection
        1. 10.3.10.1 Current Limit Setting using RILIMIT
        2. 10.3.10.2 Buck Average Current Limit Design Example
        3. 10.3.10.3 External MOSFET Gate Drivers
        4. 10.3.10.4 Cycle-by-Cycle Buck Current Limit
      11. 10.3.11 IEC and Overvoltage Protection
        1. 10.3.11.1 VBUS and VCSN/OUT Overvoltage Protection
        2. 10.3.11.2 DP_IN and DM_IN Protection
        3. 10.3.11.3 CC IEC and Overvoltage Protection
      12. 10.3.12 Cable Compensation
        1. 10.3.12.1 Cable Compensation Design Example
      13. 10.3.13 USB Port Control
      14. 10.3.14 FAULT Response
      15. 10.3.15 USB Specification Overview
      16. 10.3.16 USB Type-C® Basics
        1. 10.3.16.1 Configuration Channel
        2. 10.3.16.2 Detecting a Connection
        3. 10.3.16.3 Configuration Channel Pins CC1 and CC2
        4. 10.3.16.4 Current Capability Advertisement and VCONN Overload Protection
        5. 10.3.16.5 Plug Polarity Detection
      17. 10.3.17 Device Power Pins (IN, CSN/OUT, and PGND)
      18. 10.3.18 Thermal Shutdown
      19. 10.3.19 Power Wake
      20. 10.3.20 Thermal Sensing with NTC (TPS25833-Q1)
    4. 10.4 Device Functional Modes
      1. 10.4.1 Shutdown Mode
      2. 10.4.2 Standby Mode
      3. 10.4.3 Active Mode
      4. 10.4.4 Device Truth Table (TT)
      5. 10.4.5 USB Port Operating Modes
        1. 10.4.5.1 USB Type-C® Mode
        2. 10.4.5.2 Standard Downstream Port (SDP) Mode — USB 2.0, USB 3.0, and USB 3.1
        3. 10.4.5.3 Charging Downstream Port (CDP) Mode
        4. 10.4.5.4 Dedicated Charging Port (DCP) Mode (TPS25833-Q1 Only)
          1. 10.4.5.4.1 DCP BC1.2 and YD/T 1591-2009
          2. 10.4.5.4.2 DCP Divider-Charging Scheme
          3. 10.4.5.4.3 DCP 1.2-V Charging Scheme
        5. 10.4.5.5 DCP Auto Mode (TPS25833-Q1 Only)
      6. 10.4.6 High-Bandwidth Data-Line Switches (TPS25832-Q1 Only)
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1  Output Voltage
        2. 11.2.2.2  Switching Frequency
        3. 11.2.2.3  Inductor Selection
        4. 11.2.2.4  Output Capacitor Selection
        5. 11.2.2.5  Input Capacitor Selection
        6. 11.2.2.6  Bootstrap Capacitor Selection
        7. 11.2.2.7  VCC Capacitor Selection
        8. 11.2.2.8  Enable and Under Voltage Lockout Set-Point
        9. 11.2.2.9  Current Limit Set-Point
        10. 11.2.2.10 Cable Compensation Set-Point
        11. 11.2.2.11 LD_DET, POL, and FAULT Resistor Selection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Ground Plane and Thermal Considerations
    3. 13.3 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 サポート・リソース
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.3.14 FAULT Response

The device features an active-low, open-drain fault output. Connect a 100-kΩ pullup resistor from FAULT to VCC or other suitable I/O voltage. FAULT can be left open or tied to GND when not used.

Table 10-4 summarizes the conditions that generate a fault and actions taken by the device.

Table 10-4 Fault and Warning Conditions
EVENTCONDITIONACTION
Overcurrent on OUTNFET or Buck average current limit implemented per Current Limit Sensing using RILIMIT.

ICSN/OUT > programmed ISNS.

The device regulates current at ISNS either by external NFET or by the buck regulator control loop.
When current limiting by external NFET, there is NO fault indicator assertion under minor overload conditions.
When current limiting by buck average current, there is NO fault indicator assertion under minor overload conditions.
Hard shorts during average buck current limiting may trigger buck hiccup operation. The FAULT indicator asserts immediately after NOC cycles in and persists for TOC as specified in Cycle-by-Cycle Current Buck Limit.
Overvoltage on BUSVBUS > VBUS_OVThe device turns on the BUS discharge path in the event of an overvoltage conditions, and turn off the LS_GD immediately. The FAULT indicator asserts and de-asserts with a 8-ms deglitch.
Overvoltage on the data linesDP_IN or DM_IN > VDx_IN_OVThe device immediately shuts off the USB data switches. The FAULT indicator asserts and de-asserts with a 8-ms deglitch.
Overvoltage on CC linesCC1 or CC2 > VCCx_OVThe device immediately shuts off the CC lines. The FAULT indicator asserts and de-asserts with a 8-ms deglitch.
Overcurrent on CC lines when supplying VCONNILOAD_CCn > IOS_CCnThe FAULT indicator asserts and de-asserts with a 8-ms deglitch. The FAULT indicator remains asserted during the VCONN overload condition and the VCONN path is not disabled.
TPS25833-Q1 External over-temperature detection (NTC)VNTC ≥ VWARN_HIGHThermal warning flag THERM_WARN asserts immediately. Also the Type-C advertise current will change to 1.5 A if operating with 3A originally. The FAULT flag is not asserted for this condition, but will assert for conditions stated in this table.
TPS25833-Q1 External over-temperature detection (NTC)VNTC ≥ VSD_HIGHThe device immediately shuts off the buck regulator, opens the USB data switches, while simultaneously pulling LS_GD and BUS low. The THERM_WARN indicator remains asserted.